On page 97 of the datasheet it is written that the "slave accepts data from an external master up to 5.12 Mbps." This appears to conflict with the minimum value of the data input hold time tDHD, on page 13, table 5, which is specified as 2 x tUCLK. Given that tSL must be at least tDHD (minus the duration – which can be negative – SPI masters keep the data valid on the MOSI line after the output changing SCLK edge), the clock period may not be shorter than
2 x tDHD = 2 x 2 x tUCLK ≈ 391ns which results in a max. bitrate of 2.56 Mbps. This is only half of the value given on page 97.
If I am not doing something wrong in my calculation, which of these max. frequency values is the correct one?
The ADuC7061 (at least the piece that I'm testing), by the way, appears to accept data even at 7.5MHz, which suggests a smaller minimum tDHD value.
Thanks for high-lighting that conflict - on short 5.12 Mbps have been tested to work.
We will check the details and update this in a future revision of the data-sheet.
since Rev. F of the datasheet is public for a while now, and I'm currently working on a project using ADuC7061's SPI slave, I've had a look at this issue again. Tables 5 and 6 (pp. 13, 14) of the datasheet have been updated, so that for both tSL and tSH now the minimum value of 2 x tUCLK is listed. This results in a maximum bitrate of
f = 1 / (tSL + tSH) = 1 / (2 x 2 x tUCLK) = 1 / (2 x 2 x 97.6ns) = 2.56 Mbps.
On page 97, near the top right corner, though, still 5.12 Mbps are noted for slave mode. As you have written, 5.12Mbps have been verified.
On the other hand, on the top left corner on the same page, a maximum bitrate of 2.56 Mbps is listed -- this has been changed between rev. E (5.12Mbps) and rev. F (for master mode, this makes zero an invalid value for SPIDIV, btw.).
Which bit rate value is right for slave mode: 2.56 Mbps or 5.12 Mbps? As I want to use the maximum possible SPI slave bitrate in my current project, I would be glad if this could be clarified.
It's possible that the bit rate can up to 5.12Mbps in slave mode. Because the clock is sent from the master, not ADuC706x. I am not sure the details of your application, I suggest you doing test if there are several 8-bit data received in one period of SS pin being low. I am not sure if the 5.12Mbps is suitable for this kind of case.
the ADuC706x's SPI slave as such is perfectly working for me; I'm using it in various projects with quite different setups, and it appears to work (in an experimental setup) even at 7,5 Mbps quite stable with the full fifo size of 4 bytes, as I've tested two years ago.For me its more about trying not to misinterpret the specification, that was adjusted in this context in 2/2017. I totally understand that the clock, in slave mode, is sent by the master. What I wanted to point out, is just that if -- according to the SPI slave timing tables in the datasheet pp. 13, 14 -- the duration of low and high pulses of the external clock in sum may not be less than 4 x 97.6ns, the maximum specified external master's spi clock frequency may not exceed 2.56 Mbps. As this is only half of the value listed near the top right corner on page 97, 5.12Mhz, this leaves me with the impression of an inconsistency, but maybe I'm just overlooking something.