ADuC7023,Reduce the chip frequency will have any effects on I2C communication?

In use ADuC7023 chip as slave, there is the I2C communication unstable phenomenon.
Please help to confirm:
 
1. ADuC7023 in 10.44 MHz kernel clock frequency(POWCON0) as slave whether support the I2C standard mode (100 kHz) communications?
2. Reduce the chip frequency will have any effects on I2C communication?

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    •  Analog Employees 
    on Aug 2, 2018 4:03 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin
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  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:03 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin
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