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SER(soft error rate) and HCI(hot carrier injection) of the ADuC7023

jhshin
on Dec 5, 2019

Hello all,

Is there any information about SER(soft error rate) and HCI(Hot Carrier Injection) stability of the ADuC7023 ?

Could you please provide the data ?

Thanks.

  • 0 on Dec 12, 2019 9:00 AM over 1 year ago

    Hello,

    Still waiting for a feedback regarding my customer request..

    Regards,

  • 0
    •  Analog Employees 
    on Dec 26, 2019 7:23 PM over 1 year ago in reply to jhshin

    HI,

    We don't have hot carrier injection data for this device.

    The ADuC7023 is developed on a 250nm fabrication process - the transistor sizes on this process are less susceptible to soft errors than devices on lower transistor geometry processes. This is because the critical charge level required to flip a bit or glitch a flip-flop is higher on the ADuC7023.

    For the Soft error rates:

    The Industrial standard SN29500-2:2010-09 note 2 states “For sporadic failures, a failure rate of up to 1000 FIT/Mbit can be expected”.

    The industrial standard, IEC 61508-7:2010 section A.5 gives a soft error rate in the range 700 Fit/Mbit to 1200 FIT/Mbit.

    The ADuC7023 has 64kB or Flash, 8kB of SRAM = 73726 bits.

    Using a 1200 FIT value per Mbit, this gives a FIT value of 88.47 (failures per billion hours of operation).

    A FIT value for the flip-flops and other digital logic is not included but is expected to be small.

    Hope this helps, 

    Regards,

    Mikel