According to the ADuC7020 datasheet on reset P0.6 (pin 19) function is MRST and kernel changes P0.6 default configuration to GPIO. Should I see about 128 ms delay between IOVdd and MRST rising edges during power up? According to my oscilloscope the delay is only 100us. Am I missing something in the datasheet regarding power - on reset operation?
Answering to myself: My mistake, apparently P0.6 is pin 11 which is MRST signal and it is delayed about 120 ms during power up event. Pin 19 has ~RST function and only can operate as input for device external reset.