The datasheet of ADuC7023 shows that "If RSTSTA is null, the reset is external."I want to confirm that when RSTSTA is null after reset, does the external reset must be caused by the RESET pin being pulled down?In other words, is there any other possibility that RSTSTA is empty after reset?
In order for the RSTSTA to become cleared, RSTCLR register must be configured on its corresponding bit. However, if RSTCLR is not configured at all, RSTSTA bit will always be set to "1" once POR or any reset method occured. This is also listed as a default value for RSTSTA register.
Thank you for your reply,
There is an abnormal reset during use ADuC7023. RSTCLR was not operated after reset, but RSTSTA showed 0x00. I will operate RSTCLR after reading RSTSTA.
I'd want to know what is the reason for the abnormal reset except external hardware reset.
In addition,I found that there is a requirement for IOVdd in the datasheet "Frequency noise greater than 50 kHz and 50 mV p-p on top of the supply causes the core to stop working. "
Will a reset occur in this case? What is the state of RSTSTA at this time?
Suggested would be to use RSTCLR to reset RSTSTA. You can try to do software reset and see if RSTSTA bit will be present though normally, externally resetting the part would have RSTSTA to 0x1.
For your second question, this relates to AC Power supply rejection. Noise on IOVDD of this frequency and amplitude can cause the PLL to lose lock. I believe it has nothing to with the RSTSTA register. A data/Prefetch abort or other ARM fault exception is more likely to happen.