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### Q

In A/D timing for ADuC812 normaly I use low frequency of sample ( 50Khz and
lower) In DS AD declare that Frequency of A/D is MCLK / CK1,CK0 bit  plus
AQ1,AQ0  table value
If I use 16Mhz clock I have a T of 1/16e6  = 62.5nS

One A/D conversione need of 16 ADC clk;
If I selecting CK1 and CK0 to zero MCLK divider is 1 .
Than for A/D conversion timing is (62.5ns  x 16 ) plus AQ1, AQ0 table value
If I select AQ1 = 0 and AQ0 = 1  my final value is :
(62.5ns x 16 ) + (62.5ns x 2)  = 1uS + 125ns = 1,125nS
This is value for 888Ksps!!
A/D on chip for AduC812 have a target for 200KspS or 5uS
My question is : Value of sample rate more higher that 200Ks are dangerus then
customer never must use this value ?

### A

The ADuC812’s successive approximation ADC is driven by a divided down version
between 400KHz and 4MHz., and optimum performance is obtained with ADC clock
between 400KHz and 3MHz. Frequencies within this range can easily be achieved
with master clock frequencies from 400KHz to well above 16MHz with the four ADC
clock divide ratios to choose from. For example, with a 12MHz master clock, set
the ADC clock divide ratio to 4 (i.e. ADCCLK = MCLK / 4 = 3MHz) by setting the