Question
HMC1082LP4E - Part Configuration, Architecture & Biasing Details
Answer
Why is there 3 different drain voltage pins, but only a single gate voltage pin? Can you perhaps provide me with more details of the amplifier'scircuit diagram?The HMC1082LP4E is not a cascode distributed amplifier but rather a three (cascaded) gain stage single-ended power amplifier. Each of the three gainstages has its own drain pad, corresponding to the three Vdd pins on the package. All three of the gain stages share a single gate voltage, thus thesingle gate pin.
The only information regarding the allowed range of Vgg is the footnote below the Electrical Specifications table. What is the absolute maximum range(both negative and positive) of Vgg that will not cause permanent damage?I would need to check with Design in order to obtain a definitive answer to this question. I can immediately answer that pinch-off (i.e., the drainleakage current while the transistors are “off”) is tested in production using Vdd=5V and Vgg=-2.5V…so bringing the gate as negative as -2.5V isdefinitely safe under those conditions. To obtain the target Iddq=220 mA @ Vdd=5V typically requires a gate voltage of approximately -0.7V. Therewill be some lot-to-lot and part-to-part variation to that value so, the Vgg required could be up to several tenths of a volt higher or lower. Theproduction test searches for target bias Iddq=220 mA @ Vdd=5V by varying Vgg between -1.5V and 0V. If Iddq=220 mA cannot be obtained within thatrange of Vgg, then the part fails. For that reason it can be assured that the customer will never need to apply Vgg>0V to obtain Iddq=220 mA. Is thatinfo adequate for answering your question ? (Safe gate voltages are likely to also have dependence upon Vdd)
What is the input impedance of the Vgg pin? Is it a very high impedance that can be driven by a circuit with a relatively high output impedance(~5kOhm)?The input resistance of the Vgg pin is >>5k ohms. Some production test data I just reviewed shows pinch-off gate currents of magnitude << 0.01 mAwhile Vgg=-2.5V…though the production test allows the use of DC supplies that might not accurately measure the gate current. For that reason I willsay that we don’t have reliable data from which to accurately calculate the Rin of the gate pin. Using a source of relatively high output impedance(~5k ohm) should work fine for driving the gate, at least at small signal RF conditions. As RF Pin is increased toward saturation the gate currentmagnitude can increase somewhat so, if they plan to operate near saturation then they might want to evaluate performance using their relatively highoutput impedance (non-stiff) gate source. How much that gate current changes with Pin has some dependence on the frequency of operation.
What is the correct power-up and power-down sequence and biasing for this device?http://www.analog.com/media/en/technical-documentation/application-notes/AN-1363.pdfhttp://www.analog.com/media/en/technical-documentation/application-notes/mmic_amplifier_biasing_procedure.pdf?doc=hmc8118.pdfFrom AN-1363, use the HMC1131 Biasing and Sequencing Requirements.From MMIC Amplifier Biasing Procedure, use the Standard Amplifier Bias Sequence.
In all applications of this type of amp an important goal of the gate bias procedure is to keep the gate under control such that the drain currentnever increases to a value that could result in damage to the part due to overcurrent or excessive Pdiss.That goal can be achieved in a number of ways. Applying bias using a particular sequence is the typical way.
