First, it's important to understand how the feedback loop in the MAX9612 operates to drive an external FET gate voltage to a set point. In the datasheet, an application diagram for biasing a base station is given, using an external 10-bit DAC to adjust the settling voltage. Looking at the functional diagram of the MAX9612, the current sense amplifier is connected to the inverting terminal of an internal op amp. Assuming the system is in a steady state, if the voltage at OUT increases, the external n-channel FET gate voltage increases, which will cause the drain current to increase, which will increase the differential voltage across the current sense resistor, which will increase the voltage at the internal inverting terminal of the MAX9612 op amp, which will cause the OUT voltage to decrease. This confirms that the circuit in datasheet figure 4 operates with negative feedback.
With this type of feedback, the op amp will try to drive the circuit until its two input terminals have an equal voltage. The non-inverting terminal is directly connected to the SET pin, and is tied directly to the external DAC output. The inverting terminal is connected to the output of the current sense amp, so its voltage is equal to 2.5*I_DRAIN*R_SENSE. Thus the DAC can be used to set the control point as follows:
I_DRAIN = V_DAC/(2.5*R_SENSE)
The external FET's characteristics will relate its drain current to gate voltage, so that depends on the FET selection. That relation, in addition to the equations given in the MAX9612 datasheet for V_GATE as a function of V_NEG, V_CLAMP, and R1, R2, R3, and R_SENSE, should be used to design the control loop. There are not additional guidelines for choosing the R_SENSE value, other than sizing it so that the full-scale voltage (which is dependent on the MAX9612 gain setting) is not exceeded.