AD8488 applications questions

Hi,

I have contacted the responsible Apps Engr of this part and we will provide feedback the soonest.

Thanks!

Hi,

I got a response from the responsible Apps Engr and here are the answers to your questions.

• How do we tune the integration time beyond 12µs? From my point of view, we must use the HOLD pin and let it at the high state for a longer time. Am I correct? And is there a maximum limit for the integration time?
  • The integration time can be 12µs or greater. The integration time is 12µs (180 CLKs) when the clk frequency is 15MHz. For a 15MHz clock, the period is 66.67ns. 66.67ns/clk*180clks = 12µs. When the clk frequency is lower than 15MHz, for example 1MHz, the integration time would be 1µs/clk*180clks = 180µs.
  • In order to keep the timing diagram the same, for a given clk frequency, the time needed for integration is 180 clocks, therefore you should not just increase the time the HOLD pin is high in order to increase the integration time. The gate line sequence requires 405 clock cycles for channel integration and sequential transfer to an ADC.
  • The designer of the part mentioned the AD8488 can be used with a long acquisition time (on the order of ms, by lowering the clk frequency to 100kHz). In this scenario though, the input leakage current would be a factor to consider.

• If we want to slow down the output mux is it possible to slow down the clock (bellow 1MHz) during the output phase?
  • The read out clock could be as slow as 100kHz, but at the slower clock, there may be additional errors due to 1/f noise of the sample and hold circuitry.

• Do you have more explanation or information about the usage of the /WR pin? In the Figure 18 is mentioned a data line but I do not understand where I can access this data line and what am I supposed to send?
  • The WRB pin is a digital logic pin.
  • In order to write data, sequence the WRB pin low, then high. WRB (i.e. /WR) is ball number G14 on the AD8488. Figure 18 shows the timing diagram to write a static signal to Channel 0 to Channel 63 or Channel 64 to Channel 127.
  • For example, if you would like to change the integrator capacitor content to 7.0pF for Channels 0 through 63, you would apply a logic level 0 to /CS_A and apply a logic level 1 to pin CF1SEL1 and logic level 1 to CF1SEL0, then sequence the /WR pin LOW then HIGH. 

• On page 3 of the datasheet I see that the CCR have a very large span +/- 26% which is quite huge. I was wondering if it is possible to do a calibration on one of the 128 channel and then applied it to all. I am basing this hypothesis on the fact that Figure 7 show a very stable value of CCR across the 128 channels.
  • Yes, you could do a calibration on one of the 128 channels. The channels all match pretty well based on what is shown in Figure 7.

• Is the signal TFT_GATE an internal signal?
  • The TFT_Gate is a signal generated from the detector panel array. According to the timing diagram, when the clk frequency is 15MHz, the TFT_GATE signal should remain low for at least the 6.1µs when GRST is high so the AD8488 can sample the noise and cancel out Vos internal to the part before the charge of each detector cell is applied to the AD8488.

• When the SWIRST and CF switch are open, what is the leakage current on the analog input?
  • The input leakage current is shown in the section of the spec table below:
  • 
• Do you have an application schematic with the ADC?
• 

• Do you have a procedure to perform a current calibration of the channels
  • I do not currently have a documented procedure to perform a current calibration of the channels.

Thanks and regards.