LT spice simulation for LT1991

Hi Ashish,

The simulation results you're seeing are completely accurate.

The output distortion that happens at higher input frequencies is due to the slew rate limitations of the LT1991. In addition to the limits of gain-bandwidth product, the output's responsiveness is limited by its slew rate. No op amp output is able to immediately go from Vee to Vcc, it always needs some finite time to catch up (charge carriers in semiconductors do not travel at infinite speed!). Thus, we have a limit in how far the output voltage can move in a given amount of time. That limit is slew rate, and it has units of V/s. 

If you measure the slope of the output's rise with an input of 5V amplitude (10Vpp) and just 5kHz, the slope is 117172 V/Hz, or equivalently, 0.117V/us (circled in red in the sim results below). Our stated slew rate spec is 0.12V/us typical. The part is therefore hitting its limit, and the output can't possibly rise fast enough to respond to the changing input.

If you need this input speed and amplitude, you will have to use a different part with a higher slew rate to keep up. But if the part will rarely be asked to go from -5V to 5V, you can limit the amplitude range and thus reduce the demand on slew rate. Just reducing the input signal a bit (ie 4V amplitude, 8Vpp) at the same frequency will allow it to slew all the way to completion and not distort the output (slope = 106610 V/Hz, or equivalently 0.106V/us slew rate).

Also, the delay you're seeing in responsiveness at higher frequencies is correct as well, because the part has a finite step response and rise/fall time. In the example for 8Vpp, 5kHz, the delay between the input (blue) and output (green) is only 5us, as circled in red below. Our spec says rise time/fall time is 3us typical, so this is in the ballpark of what is expected. Once again, there is never going to be a part that perfectly completely tracks the input with no delay at all, since charge carriers travel at finite speed in silicon.

Please let me know if you have further questions about LT1991.

Best regards,

Catherine

Thank you so much Catherine for the explanation. It is really very helpful.

Hi Catherine,

I found one more device LT1997-2 seems to be suitable for my application (Slew rate 0.45 - 0.75 V/uS). If I set the gain 0.3

1. It is working fine for all input range and frequency of 10KHZ for Sine wave.

2. I can see Overshoot and undershoot at rise and fall for Pulsed wave V(out). This behavior I did not see with LT1991. Pulse Specs: 

Could you please provide your comment.

Thanks

Hi Ashish,

The overshoot you're seeing here is caused by the specified rise/fall time of 1ns in your input square wave, combined with the very extreme 0-to-10V step you're applying. If you relax the rise/fall time to 5u/10u for this large-signal input, LT1997-2 can respond without overshoot.

This part's -3dB bandwidth is ~1MHz, and that's assuming small signal, not a full 0 to 10V leap. A rise time of 1ns requires a GHz-range or higher BW to track it accurately. The output is heavily slew limited too, since the slew rate of this part is 0.75V/us or roughly 750kHz. What you're asking it to do is more like 2*pi*(10V*0.3)/10ns = 18.8V/ns slew, which is 25000x faster.

Since the sharp corner of an ideal rising or falling edge is moving infinitely quickly (rise rate = (some nonzero V)/ (0 time) = infinity), you would need infinite bandwidth to be able to faithfully track and reproduce it. Thus, in real circuits, some degree of overshoot/undershoot is always inevitable in a step response, it's only a matter of how much and for how long.

If the part is struggling to keep up like LT1991 was, there won't be a significant overshoot, because the output is so delayed that it acts as filter of sorts to remove those high frequency components, and all the sharpness is rounded out.

There is a tradeoff of settling time vs overshoot magnitude - if it overshot less, it would also take longer to settle to its final value, which means you'd have to wait longer to have a reliable reading to sample or measure.

The 0.1% setting time specs for LT1997-2 are in the 15-20us range, which means the earliest you can count on the output being off by at most 0.1% from its final fully-settled value is 15-20us after output has begun to respond. If less accuracy is required, you can safely sample sooner than 15us after.

As long as the magnitude of overshoot won't break things or cause errors, most designs will optimize for faster settling time, since the slowest response in the system will limit the overall system's response speed. If 0.1% settling output accuracy is strictly required, for instance, an ADC with 100Msps sample rate would be overkill, since it would mostly be sitting around waiting for 1997-2 to finish settling so it could sample its output.

Please let me know if you have further questions.

Best regards,

Catherine