ADHV4702-1 Frequently Asked Questions

  • Hello bgbeucler,
    now that we have tested the ADHV4702-1 with the new PCB Design, we got another problem with the HV Supply. We are using two LT8365 Converters for the negative and positive HV Supply Rails. Under certain circumstances some of the boards are working fine while others do not. There is a sporadic failure for which we have no explanation yet. By chance, can you also support this topic? I asked some questions in the associated Engineer Zone Category once, but the response activity was quite less. If so, I would like to give you a detailed description of the problem.

  • Thanks for the feedback Chrisbo.  Don't hesitate to reach out if you have any ore questions or problems.

  • Thank you for your response! We were aware that there is parasitic capacitance to charge and discharge. We tried to minimize this with cutting out the ground plane where the large signals take path, letting the signals paths as short as possible and using tracks with a width just as necessary. But okay, maybe there is still significant parasitic capacitance and like you described, we mistargeted the purpose of the Radj feature anyway.
    So, in a second design of the PCB, we improved the driving capability of the HV Supply by using a different step-up converter than before with a higher switching current. Also we are using bigger coils now with lower resistive losses so that the overall performance was significantly improved. In that way, is it possible to drive the HV stages with a shorted Radj. The PCB will be manufactured and tested soon. Thank you for your help and explanations!

  • Hi Chrisbo, thanks for reaching out on this.  Great question!  The issue here is that, despite the piezo structure requiring very little power, you are still supplying a large dynamic signal which requires lots of large signal bandwidth.  Large signal BW involves charging and discharging capacitive nodes in the signal path, and that in turn requires substantial quiescent current. The Radj feature is a power-saving feature aimed at DC applications where precision and high voltage are needed, but not bandwidth.  Slew boost is not a substitute for bandwidth, as it only affects the output stage.  The nodes 'upstream' that tell the output stage what to do simply don't have the bandwidth for what is being asked of them.  I'd suggest (at least as an experiment) to reduce the value of Radj and see how the performance improves.  Please let me know what you find.

  • Hi,
    we are using the ADHV4702-1 for driving a piezoelectric MEMS structure. Hence, this application requires a large scale sine voltage (+/-110 rail-to-rail). After a preamplification the ADHV4702-1 gains the signal by a factor of 10. Since the piezoelectric structure has a very low power consumption, Radj is set to the maximum recommended value of 100kOhm to reduce bias current. As we increase the signal frequency beyond 3kHz, the bias current rises from 600µA to 1,2ma at 5kHz. We measure a phase shift of 2-3° resulting in a difference voltage of about 1 Volt at the OpAmps input (clamping diodes begin to clip). We assume, that the Slew Boost Circuit takes effect at that point, although we are using clamping diodes to reduce the Slew Rate. The bias current increases and given that, the Supply Voltages of +/-110V drops due to the limited driving capability of the Step-Up Converters. Do we have a correct setup for the application of the ADHV4702-1 to support a large scale sine voltage? Why does this phase shift of 2-3° appear? Is the bandwidth reduced that high because the bias current is limited with Radj? (Otherwise, that would result in increased bias current because the Slew Boost Circuit takes effect.)
    Thank you for your response!