LTC2064 High side current sense circuit-Clarification required

Hi Hari,

I already forwarded your concern to the product owner of this part. I'll get back to you as soon as I get the information you need.

Hi Hari,

Thanks for your question! Unfortunately, the circuit that you have drawn shorts out all of the active components, so the output would always be a constant voltage set by the resistor divider between RIN and Rload.

My best guess is that you may be confusing this high-side current sense circuit with an op-amp + FET output current source/sink architecture. The PMOS in this circuit is not to boost the output current, but to present a low-impedance current source that passes the current in RIN to the output.

In case you're interested in how the high-side current sense circuit is supposed to work, I've included a full explanation below. Feel free to skip it, or ask for further clarification.

Best regards,

Catherine

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How This High Side Current Sense Circuit Works

(I'd recommend following along on the schematic, going from left to right.)

Rsense is connected in series between the supply (Vsupply) and the burden circuit (Vburden) that is drawing current from it. This is a unidirectional current sense, so Vsupply > Vburden.

The current to be sensed (Isense) drops a voltage across Rsense:

      Vsense = Rsense * Isense = Vsupply - Vburden

There is no current in R1, since it dead-ends into +IN of the op-amp. Thus, there is no voltage drop across R1, so

      V(+IN) = Vburden

Since op-amps want V(+IN) and V(-IN) to be equal, the op-amp wants 

      V(-IN) = Vburden

But how does the op-amp get there? It just so happens that there's a handy resistor RIN between Vsupply and -IN. If the op-amp could just drop some voltage across it, by running the exact right current, -IN could be lowered to meet +IN, and the op-amp would be happy.

Since the -IN is a high-impedance dead-end, there needs to be another current path connected to RIN that is also under the op-amp's control, which is where that PMOS comes in. The op-amp can control the PMOS's current because its output is tied to the PMOS's gate. The op-amp thus produces an output to make the PMOS pull a current from the supply, through RIN, and into its source such that, when it passes through RIN, produces a drop that will set -IN to be the same as +IN.

The voltage drop across RIN is given by

      Vsupply - V(-IN)

Since we established already that V(-IN) = Vburden, the drop across RIN is also equal to Vsupply - Vburden. But wait, that's familiar! That's Vsense!

The op-amp created the drop across RIN by creating a current through the PMOS and the RIN that is a scaled-down version of the sense current, proportional to RIN and Rsense. Let's call that current Iout. To calculate exactly what it is:

As we just established, the voltage drop created by Iout is:

      Vsense = RIN* Iout. 

Going back to the definition of Vsense from before, 

      RIN * Iout = Rsense * Isense

Rearranging to solve for Iout,

      Iout = (Rsense/RIN) * Isense

Iout leaves the drain of the PMOS as the output current, and gets converted back to a ground-referred voltage when it goes through Rload. 

      Vout = Rload * Iout.

Putting in the equation for Iout from earlier,

      Vout = Rload * (Rsense/RIN) * Isense

Hi Catherine,

Good day...

Thank you very much for the explanation. I assumed in the wrong way

As per my knowledge R2 is for stability, correct me if I am wrong, may I know how to design R2.

May I know the purpose of M2, D1, REF, and C1, and also how to design the same.

Regards

hari

Hi Hari,

You're welcome! Glad that was helpful.

Before I answer your questions, I have to correct something - I misspoke when I said the output PMOS was a low-impedance current source, it's actually a high one dynamically, although its Rds,on is very low.

Yes, R2 is for stability. I kind of overdid it with R2 here, it doesn't have to be nearly that big, since this circuit is actually very stable and won't ring for a wide range of R2's. You can see more about stability analysis with regards to that resistor here: High-Side Current Sensing | Analog Devices 

M2, D1, REF, and C1, along with R3, are there to protect the LTC2063/4 from high voltages and allow this circuit to monitor a wide range of supplies, up to 90V in this case. 2063/4 has an abs max supply of 5.5V, so normally that would be the upper limit of supply voltage it can monitor. Luckily, it also operates with Vsupply as low as 1.7V, and runs on 1.4uA, so almost any voltage reference can easily serve as its power supply. That's what REF is doing in this case.

By using REF to create a little "hanging world" that shares the common top rail with a high-voltage supply but isolates the LTC2063/4's "ground" from true ground, the part's supplies can rise and fall with the overall supply to stay operating as a high-side current sense, while the reference creates a separate ground that is within a safe operating range for LTC2063/4 from the supply. In this case, LTC2063/4's rails are around 3V (4.096V from REF - diode drop from D1).

With this design, the only limit on input supply voltage is the Vds limit on M2, since M2's job is to drop the remaining supply voltage (Vin - around 3V) and serve as a "ground" for the 2063/4 and reference. BSP322P has a max Vds of 100V, so I set the input limit at 90V for a safety margin, although the circuit survived just fine when I took it to 100V in lab. M2 doesn't have to be a high-voltage device if the expected input voltages aren't that high. C1 provides supply bypass for this "hanging world."

R3 sets the bias current in the ref (LT1389) because it needs some current (~1 uA) to operate. D1 isolates R3 from LTC2063/4 and protects its negative supply if R3 somehow fails short. 

Please let me know if you have any further questions.

Best regards,

Catherine

Hi Catherine,

I tried to do the DC analysis of this circuit to find the voltage at each node during steady state condition. My assumption is V_IN=4.5V and I_SENSE = 1mA. Not able to attach word or PDF doc so  Attaching the image along with this mail, which contains my doubts. Expecting your valuable suggestions to understand this circuit more to a beginner.

Regards

Hari

Hi Hari,

I'll help answer your detailed questions later, but in the meantime please download and run LTspice simulation of this exact circuit, which can be found on the product page under "Tools & Simulations." I think looking at some sim results will help you understand the circuit better.

http://www.analog.com/media/en/simulation-models/LTspice-demo-circuits/LTC2063_DN1045_HighSideIsense.asc 

Sizing C2 and C3 is addressed in DN1045, which goes into more advanced details about this design. C3 is not strictly necessary if C2 is already there. I added a range of values so it would be easier to customize by disconnecting C3 or C2 depending on what frequency I wanted to pass.

http://www.analog.com/media/en/reference-design-documentation/design-notes/dn1045fb_web.pdf 

Best regards,

Catherine

Hi Catherine,

Done the simulations.Could you please tell me how 2.3V is obtained at the source of M1

Regards

Hari

Hi Catherine,

I changed the above schematic according to our requirement.

Separated opamp supply and current sense supply. For low values of current sense supply, the o/p is not coming properly.

Please see the figure below. If you don't mind could you please check the below circuit also