To instead of my customer posting a few questions
Question 1.
The LT6559 data sheet has mentioned If using CMOS open-drain logic, an external 1k pull-up resistor is recommended to ensure that the LT6559 remains disabled regardless of any CMOS drain-leakage currents. May I know that pull-up resistor whether is absolute value or not ? if not, please provide the resistance range.
Question 2.
About the PCB placement and layout, Whether the pull-high resistor needs to close to eache enable pin of the LT6559.
Questions 3.
I cannot find out details description about the VIL and VIH of the enable pin in the data sheet of the LT6559.
Question 4.
The DC1063A demonstration board without the pull-up resistors, why ? ( https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/dc1063a.html )