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AD829 stability

Hello,

Is the AD829 stable in the following conditions ? What is the Phase Margin ?

- CL=150pF capacitor load

- RL=~1kohms resistor load

- Vs = +/- 5V

- Ccomp = 15pF to inverted input

I attached the schematic (VEE = -5V and VCC = +5V).

Can I simulate the phase margin with PSPICE and how ? Is the model realistic in theses conditions ?

Thanks for your answer,

Mathieu

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  • Hi Mathieu,

    I apologize for the delay on this response. As I mentioned, the AD829 is a very old part, and unfortunately, I would not trust the SPICE model to be reliable in simulation. However, I revisited my circuit and we are now getting the same results on our circuit, i.e. no oscillation. In addition, I brought the capacitive load up to 560pF without seeing any oscillation at the output. One of the other methods I tried to get an idea of the stability of the circuit was to apply a step input and see how much overshoot was present at a 150pF load.

    I calculated the overshoot to be about 10%, which looks to be an acceptable figure. Hopefully, this figure will be enough to properly satisfy your requirement.

    Regards,

    Kris

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  • Hi Mathieu,

    I apologize for the delay on this response. As I mentioned, the AD829 is a very old part, and unfortunately, I would not trust the SPICE model to be reliable in simulation. However, I revisited my circuit and we are now getting the same results on our circuit, i.e. no oscillation. In addition, I brought the capacitive load up to 560pF without seeing any oscillation at the output. One of the other methods I tried to get an idea of the stability of the circuit was to apply a step input and see how much overshoot was present at a 150pF load.

    I calculated the overshoot to be about 10%, which looks to be an acceptable figure. Hopefully, this figure will be enough to properly satisfy your requirement.

    Regards,

    Kris

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