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AD829 stability

Hello,

Is the AD829 stable in the following conditions ? What is the Phase Margin ?

- CL=150pF capacitor load

- RL=~1kohms resistor load

- Vs = +/- 5V

- Ccomp = 15pF to inverted input

I attached the schematic (VEE = -5V and VCC = +5V).

Can I simulate the phase margin with PSPICE and how ? Is the model realistic in theses conditions ?

Thanks for your answer,

Mathieu

Parents
  • 1 - I checked on my board, there is no oscillation with the the schematics attached on the first message. Could you please confirm that you measured an oscillation and show the print screen of the oscilloscope ?

    2 - If there is no oscillation like on my board, how can I prove that the circuit is stable if the Pspice model is not representative ?

    Please remember that in my first message, I didn't think that my circuit was not stable. I had never meadured an oscillation before.

    I just wanted to know :

    - if with this type of compensation, the AD829 was capable of driving such a capacitor load (150pF)

    - and how determine the phase margin by simulation

    Regards,

    Mathieu

Reply
  • 1 - I checked on my board, there is no oscillation with the the schematics attached on the first message. Could you please confirm that you measured an oscillation and show the print screen of the oscilloscope ?

    2 - If there is no oscillation like on my board, how can I prove that the circuit is stable if the Pspice model is not representative ?

    Please remember that in my first message, I didn't think that my circuit was not stable. I had never meadured an oscillation before.

    I just wanted to know :

    - if with this type of compensation, the AD829 was capable of driving such a capacitor load (150pF)

    - and how determine the phase margin by simulation

    Regards,

    Mathieu

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