Is the AD829 stable in the following conditions ? What is the Phase Margin ?
- CL=150pF capacitor load
- RL=~1kohms resistor load
- Vs = +/- 5V
- Ccomp = 15pF to inverted input
I attached the schematic (VEE = -5V and VCC = +5V).
Can I simulate the phase margin with PSPICE and how ? Is the model realistic in theses conditions ?
Thanks for your answer,