Low Noise Variable Gain AD600 Amplifier

Hello Satyabrata

Thank you for contacting ADI regarding your problem.

Please explain what you are trying to do. Figure 37 is intended to illustrate an agc circuit. In case you're not familiar with such circuits, the acronym means automatic gain control, and are often used in radio receivers.

If you juat need a lot of gain you have maximum gain with the 1V applied to VG, and you would not want to use the transistor, current source, etc at all.

So please fill us in a bit. Is this an experiment for a class? Are you a student?

Best regards,

js

Hi sir,

I am a student. This is for my final year project. I need a 60 dB gain amplifier with low noise psd like 1nV/sqrt(Hz). My analog signal input is in micro Volt range and it's bandwidth is 12 MHz. So i chose AD600, as it was mentioned there by cascading the two amplifiers inside that chip, we can get upto 80 dB gain.

I had also applied 1 V directly to VG, but the thing is.after cascading connection i am not getting 80 dB, and the most interesting thing is that output signal's bandwidth i am getting is 25 times of the input one.

So please help me where is the fault or should i try some more chips?

Thank you again.

Regards,

Satyabrata

Hello Satyabrata,

I thought you might be a student and you have a very interesting project.

It seems you are confusing frequency and bandwidth, they are not the same parameter, even though they can have the same units of measure. From your email question, I cannot tell which you mean. I can assure you that the input and output bandwidth of an amplifier are essentially the same, although BW at an input is not a valid specificaiton. Since you are a student, I would suggest you consult with your educational resources for explanations of these two very different concepts, or refer to Wikipedia or a similar resource site for readily available assistance. It is beyond the scope of this website for me to explain this type of basic concept.

Best regards,

JS

Hi Sir,

Actually what i wanted to point out was that after implementing through AD600, i got output signal with frequency 25 MHz where as my input signal had a frequency of 1 MHz and amplitude of 20 mV sine wave supplied from waveform generator. Why did that happen?

So far as my project is concerned, my input signal for AD600 i am taking from the output of a PZT transducer, having amplitude in micro volt range and maximum frequency content is around 4 MHz. I need a gain around 60 dB with very less noise PSD in system.

Thanking you.

Regards,

Satyabrata

Hello Satyabrata,

OK thanks for clearing that up, it makes a big difference..

I believe you also stated that the gain control voltage was 1V. If you are applying 20mV 1MHz at the input, you will be drastically overdriving the part, assuming all your connections are OK. For 1V at the gain pin, the gain will be 80dB so your output swing would theoretically be 200V. Obviously this is impossible, however it is possible to overdrive the part. Instead of 20mV, you should be applying a few tens of microvolts. If you are grossly overdriving an amplifier the results can be anything, there is no more loop control when the amplifier is operating out of its linear range.

Another point I should make is if you are using figure 37, please note that there are no decoupling capacitors in the circuit. This is because figure 37 is a conceptual circuit, and the original author omitted any power supply decoupling for clarity.

The last questions I would have is, are you testing a physical circuit, or are you working with a simulation using a SPICE model?

Once again I would strongly urge you to check with your local resources, such as the professor or course instructor. Because I’m remote, I really have no idea what you have there for your experiments. Please use your professors, as I can unintentionally mislead you by trying to guess what you are actually doing there.

Good luck,

js

Hi Sir,

Thanks a lot for your help.

Actually its a end term project. So, nobody will help. I have simulated the circuit in Multisim Component Evaluator Analog Devices Edition.

I am attaching here the output what i got.

Attachments

1. Design of the circuit

1. Output and input signals

2. Fourier analysis (voltage in dB)

Sir, i got a gain of 74 dB with -3dB bandwidth of 10 MHz.

Please verify whether i am right or wrong from those attachments. Now should i start implementing the same with pc board?

Thanking You.

Regards,

Satyabrata

Thank you sir.

I have simulated the circuit in Multisim Component Evaluator Analog Devices Edition.

I have attached the design,output-input characteristics in my last reply to jstaley sir.

If i found it to be correct, i"ll implement that on pc board.

Thanking you.

Regards,

Satyabrata

Hello Satyabrata,

As I mentioned earlier, I believe you are misusing the term bandwidth. You have not shown a frequency response curve, which is the standard way of represnting bandwidth. Figure 4 in the ds is an example of such a curve. If you were to plot such a curve, the 3dB bandwidth would be about 17MHz, as you have two AD600s in series.

Your plot of output vs input looks better, It shows about 74 dB gain, which might be accurate since you're loading the output with 50 ohms.

I'm sorry to hear you have onone to help you there. In this event, I've found Wikipedia to be a very good. There are also other websites out there with complrehensive assistance where you need a lot of basic information. I would not recommend that you commit the design to a pc board without consulting a local mentor,

Good luck,

js

Thank you sir.

Sorry sir. I got the mistake. What i have done is i took the fourier analysis of my output curve and represented the voltage in dB.

I should take the gain(vout/vin) instead, varying frequency range.

I"ll try the same sir and let you know.

Thanking you.

Regards,

Satyabrata

Hi Sir,

I have another doubt. Whether i should say i am cascading the two amplifiers present in AD 600 chip or two AD 600 chips?

I think each of the amplifiers in the chip are called AD600. Am i right sir?

You can see in my design whenever i am selecting AD600JNZ in multisim component evaluator, 9 pin ics are coming. When i am cascading the both i have 18 pins in total, out of which 2 pins are common to both namely pin no 12 and 13(power supply). Why this is happening? Why not in a single chip all the 16 pins?

Thanking you.

Regards,

Satyabrata