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ADA4096 not clamping input in unity gain buffer test circuit

I'm testing the ADA4096-2 amplifier. The testing circuit is an unity gain buffer with a 30Hz sine signal, with dual +/- 3V supply, both amplifiers receive the same signal. I see the output is clamped correctly to the supply voltage values, however, as I increase the amplitude of the signal (>4V above the positive rail), the positive clamping starts to fail and the voltage in the positive power supply rail starts to raise. I'm attaching the image of the test circuit and the signals we are seeing (the red trace is the source signal, the yellow one is the amplifier output).

Am I doing anything wrong? I expected the clamping to work up to 32 V above and below the power rails and not to affect the power rails at all.

attachments.zip
  • FormerMember
    0 FormerMember

Mario,

  Are you talking about the output voltage rising or the power supply rail rising?

See fig 54 and 55 in the d.s.  Some slight Vout rise is normal, but if your +3V supply

rail is rising, you don't have a stiff enough supply or one that can only source current

and not sink current.  When the input voltage is high, the current gets shunted to

the rails;  see fig 53.

Harry

  • The output starts to raise along with the power supply positive rail. Your explanation makes lot of sense. The power supply is a LDO incapable of sinking current and the test circuit has no other load, so when the input voltage increases too much the current is shunted to the positive rail, increasing its voltage, as the power supply of the amplifier increases then, so does the clamping level. I missed the D1 to D4 diodes in the ADA4096 internal schematic.

    Thanks a lot.

  • FormerMember
    0 FormerMember

    Mario,

      You could put a resistor on the LDO so it sinks 50-100 mA.

    Then repeat the experiment.  If you can go higher in input voltage

    before the Vdd buss and output start rising, then that would confirm my hypothesis.

    Harry

  • Hi. I tested again but now loading the power supply up to 120 mA. Now the positive rail voltage stay stable at 3V. However, I'm still seeing the "bumps" at the top of the waveforms; they appears suddenly while increasing the input signal amplitude and they are always around 1V higher than the positive rail voltage. Is this expected? I can see in the DS the figure 54 showing the same bump (however it is very small as the input [40V] and supply [10V] voltages are higher than the ones we are using).

    In case the setup matters, we have been testing in solderless breadboards, but the ADA4096-2 under test are soldered to  MSOP to DIP breakout adapters. The tests were done with a power supply with LDO regulators but also with alkaline batteries. We tested with both a +/- 3V dual supply and with a 3.3V single supply.

    I still think this amplifier will be useful, I just need to check if the ADCs we will use can withstand that extra 1V in its inputs.

    Regards, MV.

  • This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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    EZ Admin