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AD8000&AD8001 PCB design issues

Hello,

I'm designing AD8000&AD8001 for testing purpose. The AD8000's datasheet says:"Do not use ground and power planes under any of the pins of the AD8000." Is this means that I have avoid copper of the ground (or power) plane adjacent top layer? 

Below is my baord's layers structure:(Do i have to remove some copper of the Agnd1 just under the AD8000&AD8001?)

And here is the AD8001 and AD8000 used in my new test board:

Anybody can show me an example of this?

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  • Hi Coyoo,

    Based on your stack up file, if top layer refer to layer 5, C=E*E0*S/d, then the parasitics capactor on feedback net is around 0.259pF (total about 5 pcs 0603 single pad size), then the cut off frequency by RC is 1.42GHz when use 432ohm resistor, it looks like just match AD8000 frequency respond. So if you remove Layer 5 and layer 6, it's better.

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  • Hi Coyoo,

    Based on your stack up file, if top layer refer to layer 5, C=E*E0*S/d, then the parasitics capactor on feedback net is around 0.259pF (total about 5 pcs 0603 single pad size), then the cut off frequency by RC is 1.42GHz when use 432ohm resistor, it looks like just match AD8000 frequency respond. So if you remove Layer 5 and layer 6, it's better.

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