AD8000&AD8001 PCB design issues

Hello,

I'm designing AD8000&AD8001 for testing purpose. The AD8000's datasheet says:"Do not use ground and power planes under any of the pins of the AD8000." Is this means that I have avoid copper of the ground (or power) plane adjacent top layer? 

Below is my baord's layers structure:(Do i have to remove some copper of the Agnd1 just under the AD8000&AD8001?)

And here is the AD8001 and AD8000 used in my new test board:

Anybody can show me an example of this?

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  • 0
    •  Analog Employees 
    on Feb 24, 2017 10:52 AM

    Hi Coyoo,

    I mark the area that need to be GND removed, special for feedback resistor trace nets R52 and Rxx of AD8001. Because of that R is usually around 400~1000 ohms, so it cause big RC constant, that like a low pass filter, it limited bandwidth too much. That feedback net is not 50 ohm impedance, so do't worry about GND removed cause impedance match problem. Consider your board is 10 layers, if you can provide you stack up file, it's better. If not, generall speaking, top layer reference to layer 5(AGND2), that space is enough to remove parasitics capacitor. If remove AGND2, it's better. Make sure no other signal or power cross these marked area.

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  • 0
    •  Analog Employees 
    on Feb 24, 2017 10:52 AM

    Hi Coyoo,

    I mark the area that need to be GND removed, special for feedback resistor trace nets R52 and Rxx of AD8001. Because of that R is usually around 400~1000 ohms, so it cause big RC constant, that like a low pass filter, it limited bandwidth too much. That feedback net is not 50 ohm impedance, so do't worry about GND removed cause impedance match problem. Consider your board is 10 layers, if you can provide you stack up file, it's better. If not, generall speaking, top layer reference to layer 5(AGND2), that space is enough to remove parasitics capacitor. If remove AGND2, it's better. Make sure no other signal or power cross these marked area.

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