AD8000&AD8001 PCB design issues

Hello,

I'm designing AD8000&AD8001 for testing purpose. The AD8000's datasheet says:"Do not use ground and power planes under any of the pins of the AD8000." Is this means that I have avoid copper of the ground (or power) plane adjacent top layer? 

Below is my baord's layers structure:(Do i have to remove some copper of the Agnd1 just under the AD8000&AD8001?)

And here is the AD8001 and AD8000 used in my new test board:

Anybody can show me an example of this?

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  • 0
    •  Analog Employees 
    on Feb 23, 2017 2:32 PM

    Hi Coyoo,

    For high speed signal, we have to consider parasitic capacitor, even if 1pf. It depend on pad size and distance between top and 2nd layer(GND). Each big pad is like a capacitor, remove GND under pin/pad, it can increase distance, then capacitor can be reduced. If remove all reference layer, that capacitor is minimal. If your 50 ohm trace width is same as pin/pad width, that is best situation, you don't need to remove any GND under pin.

Reply
  • 0
    •  Analog Employees 
    on Feb 23, 2017 2:32 PM

    Hi Coyoo,

    For high speed signal, we have to consider parasitic capacitor, even if 1pf. It depend on pad size and distance between top and 2nd layer(GND). Each big pad is like a capacitor, remove GND under pin/pad, it can increase distance, then capacitor can be reduced. If remove all reference layer, that capacitor is minimal. If your 50 ohm trace width is same as pin/pad width, that is best situation, you don't need to remove any GND under pin.

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