AD8000&AD8001 PCB design issues

Hello,

I'm designing AD8000&AD8001 for testing purpose. The AD8000's datasheet says:"Do not use ground and power planes under any of the pins of the AD8000." Is this means that I have avoid copper of the ground (or power) plane adjacent top layer? 

Below is my baord's layers structure:(Do i have to remove some copper of the Agnd1 just under the AD8000&AD8001?)

And here is the AD8001 and AD8000 used in my new test board:

Anybody can show me an example of this?

  • Hi.

    I don't think the removal of ground plane in the input and output pins was implemented in the EVAL-HSOPAMP-1CPZ which is primarily used as the evaluation board of AD8000. Anyhow, you can refer to the attached file. It contains all the board files of EVAL-HSOPAMP-1CPZ. You can see the layout files under 20_041825a-->worklib-->02_041825a_top-->physical-->art-->fab. It was created from Allegro.

    I'll look for the board files of AD8001 evala board and will get back to you on this.

    I also recommend you to purchase the evaluation boards so you don't have to make your own boards. It would be easier for you to just setup the board then test it.

    Regards,

    Anna

    20-041825-00A.zip
  • Hello Anna,

    Thanks for you reply me quickly.

    1. Unfortunately, i can't view the art files, for i don't have cam software. Could you help to take some pictures and show them here?

    2. Our signal link is very long, and our test board will not only test AD8000&AD8001(act as adder).

    3. Acually, i want to ask you experts below simple questions:

         1). If is it necessarry for customers to remove those groud or power plane area?

         2). If 1) is yes, then how to do it? Which region should be removed? For me, my board have severy ground and power planes. Do I just need to remove the AGND1 plane (which just under the top layer) or need to remove all ground and power planes?

    BTW, for some high speed boards, i saw just remove the plane under the surface layer (top layer) to control impedence. As below picture show:

    Best Regards

  • Hi Coyoo,

    For high speed signal, we have to consider parasitic capacitor, even if 1pf. It depend on pad size and distance between top and 2nd layer(GND). Each big pad is like a capacitor, remove GND under pin/pad, it can increase distance, then capacitor can be reduced. If remove all reference layer, that capacitor is minimal. If your 50 ohm trace width is same as pin/pad width, that is best situation, you don't need to remove any GND under pin.

  • Hi Jay,

    Thanks for you reply.

    My 50 ohm trace width is not same as the pin width, so i have to remove the GND under pin. I took the removing action as below for my new test board. Which one is better? Though the left is AD8001, and the right one is AD8000.

    I just took over the AGND1, and didn't remove the GND of AGND2 and DGND.

    Best Regard

  • Hi Coyoo,

    I mark the area that need to be GND removed, special for feedback resistor trace nets R52 and Rxx of AD8001. Because of that R is usually around 400~1000 ohms, so it cause big RC constant, that like a low pass filter, it limited bandwidth too much. That feedback net is not 50 ohm impedance, so do't worry about GND removed cause impedance match problem. Consider your board is 10 layers, if you can provide you stack up file, it's better. If not, generall speaking, top layer reference to layer 5(AGND2), that space is enough to remove parasitics capacitor. If remove AGND2, it's better. Make sure no other signal or power cross these marked area.