When using 4310-1 or 4311-1, with PD0 and PD1 pins taking values between 0V and whatever is considered logic high, does the amplifier behave reasonably? By that does it behave without going unstable or draining excessive current or requiring excessive time to go back to the normal operation or normal inactive state? I would expect the amplifier to limit the output voltage range (signal potentially clipped) or the output impedance increase or some other behaviors, but I'm ok with those, as long as the change is gradual/continuous and the operation is reasonable.
The motivation of this question is, what if PD0 and PO1 are tied together, bypassed by a capacitor and driven by a medium impedance drive so that the time constant of that RC is on the order of tens of milliseconds? Any related information and the equivalent internal circuits around PO0, PO1 pins would be appreciated.
Hi Jino, thank you for your reply but that actually didn't answer my question.
I'm asking about the behavior when the PD0/1 voltage takes an intermediate value or when they vary very slowly (like a slow ramp).
Depending on how things are controlled, some analog amps go unstable or spike the DC current. (For example, if the PD0 and PD1 affect slew rate or apparent conductance or hard clip the response in the process of complete shutdown, these things may affect the closed loop behavior. If PD pins control the bias circuit, an intermediate value may spike the current, etc... but I'm only speculating because there's no information about the internal circuit of these pins.)