ADCMP562 allows setting a latch mode which will latch the state of the comparator that exists very shortly before the latch enable is sent. This implies that when the comparator triggers on an input voltage level that it was configured to detect, the device can immediately be placed in latch mode so as to hold the output state that currently exists.
What I'd like to know is how is the latch feature customarily implemented? Can the ADCMP562 latch itself as soon as it detects a desired voltage level, doing so by having its differential outputs connected to the differential latch enable inputs?
Then, sometime later, can a second comparator (the pkg has two comparators), upon detecting some other targeted voltage level, be used to place the first comparator back into compare mode, using its (the 2nd comparator) differential outputs to disable the latch mode on the 1st comparator?
This scenario would have the latch enable inputs on the 1st comparator being driven by two sets of outputs - those on the 1st comparator and those on the 2nd comparator. This doesn't seem very practical.
So, how are the latch inputs usually 'programmed' in real time to alternate between compare and latch modes, based upon detection of a targeted input voltage?
I see the problem you have posed trying to have two COMP (ADCMP562) outputs controlling the latch enable pins.
I've attached an image where CMP2 is tied to the CMP1 latach pins through diodes while CMP1 outputs are isolated from these same latch pins through series resistors. With this arrangement, when CMP2 output switches low, it removes the latch on CMP1 and reverts back to track mode.
Please take a look and see if this is what you had in mind?
May have to use Schottky diodes for lower Anode / Cathode voltage to make sure CMP2 does not have any problem with driving the latch pins due to the silicon junction diode voltage drop. I've not tested this circuit and it's just a hunch in case it helps you.