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LTC2063 integrator - drifts to Vcc

Hi Group,

I'm working on an integrator circuit, part of which is attached. Instead of a slow drift, the output ramps to Vcc in a minute or so. Also a significant voltage (200mV) is needed to arrest the drift.

LTC2063 was used because of low offset voltage and low current <5uA. Perhaps zero drift op-amps are not suitable for this job? The LTSPICE result looks perfect though.

I have a dev board type DC2837A with the core circuit shown in the attachment. I'm feeding it at points A/B for the input voltage. It takes 50x the expected input voltage to affect the drift. The current is from a 100k resistor and a 30V variable power supply, I = V/100k = 300uA max. The variable power supply is not outside the amplifier common mode or anything.

Does anyone know if the LTC2063 is suitable for an integrator like this? Can anyone suggest a better part, bearing in mind it must be <5uA supply current?

The rest of the circuit which resets the integrator is not shown, and not fitted yet. There's no point in building the rest until the basic integrator is working.



  • Hi Rob,

    Could you clarify more about the inputs you've place on points A/B. Also, what do you mean about the 200mV needed to arrest the drift?

    If I'm understanding you completely, you want to use the LTC2063 as an integrator that ramps up to VCC in about a minute?



  • Hi Donnie,

    To correct myself, it takes 200uV across the points A/B to stop the amplifier drifting towards Vcc. The voltage is applied by a 10V power supply and 100k resistor across A/B. This gives 2/10k x 10V = 200uV on the amplifier inputs.

    The input offset of LTC2063 is specified as 10uV maximum. But it needs 20x the input offset to make the amplifier output change. That is surely not right?

    I want the integrator output to remain constant (hold) if there is no input at all. Obviously the output will drift, but under 2 minutes to go hard over seems wrong.

    I'm stripping down the DC2837A dev board today, replacing the parts and cleaning it. That will eliminate any doubts about the construction.


  • Hi Rob,

    Why both inputs of op-amp are floating in your design? The rest of the circuit pulls the non-inverting input to some potential, as is customary in integrators?

    The amplifier attempts to compensate for any differential voltage between the inputs via a feedback loop. In your case, it passes a constant current through the capacitor. If you can measure the slope of the output voltage, you can calculate current through the feedback capacitor. This will help to better understand the cause of your scheme's behavior.



  • Hi KirV

    The inputs are not floating, it's only shown that way to simplfy and avoid confusion! The inputs are mid-rail.

    The slope is about 25mV/s. That works out to far more current than should be happening with this op-amp.

    I stripped off all spare parts and cleaned the board with solvent. No difference. Some alternative amplifiers arrived today to be tested tomorrow.

    It doesn't make sense that such a high performance amplifier performs so poorly in this circuit.


  • Hi Rob,

    I think I've figured out why you're seeing these confusing outputs:

    1) The output of an R-C op-amp integrator is actually -Vout, an inverted version of the desired rising Vout signal. If you don't put in any input, and don't invert the output either, you should be seeing a high signal because that's the opposite of 0 Vin. Up high is the resting condition of the integrator output with no input applied.

    The (relatively) fast slope you're seeing there is the slew rate of the output rising to where it's supposed to be; I'm impressed it's 25mV/s because our stated spec is more like 3. 

    The reason your 200uV offset seems to bring it down from rail is because any input signal will pull the output signal down, inversely proportional to itself.

    To address this, you need another stage after this one that will do the inverting to convert the -Vout back to the desired polarity of Vout. A simple inverting amplifier will work. However, the catch is that if you're using this inverter in a single-supply configuration, it needs to be offset to mid-rail so it can pull down successfully. Otherwise, it will bottom out halfway through.

    2) Node B needs to be connected directly to GND. This is because this is the reference node for the integrator to pull against. As the inputs get bigger and bigger, the op-amp will work harder to push IN- down to match IN+, and in doing so, create a negative output proportional to the input. Thus, IN+ has to be tied directly to GND, not through a resistor, so the op-amp output can pull all the way down to the bottom. If there's a series resistor there, the voltage will not be able to go down to 0.

    This is a situation in which the balance resistor at IN+ isn't needed, since the node will be hard tied to ground anyway.

    I have attached a .zip file with an LTspice of the integrator I described plus the additional inverting output stage with offset. Please try this out and let me know what you think.

    LTC2063 Integrator +

    Best regards,


  • Hi Rob,

    it's only shown that way to simplfy and avoid confusion!

    Unfortunately, you have confused us even more. Try to redraw the circuit, showing what comes to the inputs of the operational amplifier relative to the ground, what impedances exist on these paths.



  • Hi Catherine/Kirill,

    I included a screenshot of the 2 test circuits/simulations. The 'ramp' signals in each case in reality go to V+ in under 2 minutes, not at all what the simulations predict. I know all about the basics of op-amps (of 30 years experience) but never used this device before - not surprisingly as it has only been available for under 2 years!

    The 2 situations should give similar ramp times as in the simulation but in practice the ramp going negative needs a large current thru the 2 ohms to do anything. Separating the sense resistor from +V or -V makes no difference.

    Catherine, your simulations work fine here. I'm not sure how to upload .asc files in this forum. Links to external files may work?

    The balance resistor indeed makes so little difference here it can be omitted. The simulation does report a small difference.

    Having a ramp in either polarity is not the issue, it's getting any ramp of the correct duration and to respond to perhaps 20uV of input difference. The LTC2063 spec is 5uV offset so this should be possible.

    I'm expecting a replacement LTC2063 chip soon, so can report back once it turns up.


    The design is part of a system with a lithium primary cell, 3.6V. The spec calls for measuring supply current and estimating remaining life of the cell. But, the device current varies between 20uA and 50mA. Also the current monitor itself cannot take more than a few microamps or the cell life is reduced.

    There are many gas gauges for rechargeable cells. All take >50uA and have complications in making them work at very low current.

    Here the integrator time is dependant on the current thru a sense resistor. A micro can detect when the ramp gets near complete and reset the integrator, then increment a counter. With the LTC2063 supply current is <2uA so can be left always-on.

    LTC2063 (ADI) and LPV821 (from T.I.) are the only chips that can do this job at the moment. The T.I. chip has maximum supply of 3.6V and my cell voltage is 3.6V, so right on the limit. The LTC2063 has max supply of 5.25V, and is preferred.

    Probably too much information, but should fill in gaps.


  • Hi Rob,

    So, you expect the slope of the output voltage to be significantly slower. This will be true if the integrator input floats; in this case, bias current will flow through the capacitor. You should expect a slope value in the region of 3 millivolts per second, based on the specification for the operational amplifier.

    In your case, it is not. Between the inputs of the op-amp is a resistor; note that the LTC2063 has a very high open-loop gain; the offset voltage is amplified and fed to the output; to compensate, the op-amp must pass some current through the capacitor and resistor, which form a differentiating RC network. Consequently, a slope is formed at the output, which differentiated and compensates for any impact between the inputs.

    I tested my version using the elementary model of op-amp:

    You can see that the slope is much greater than you would expect, thinking only of the bias current. To simulate turning on the amplifier, I used a surge offset voltage. Also, do not forget about the contact potentials and thermal effects, which can add a few more microvolts to the input, then the slope will be even greater than in my simulation.

    Please test other samples. It should be expected that some sample will have a different sign of the offset voltage and the slope will be negative, but just as significant. Let me know the results.

    I hope that this help you.



  • Success!

    I changed the amplifier and it produces a slope closer to the simulation. No idea what caused the other part to produce an incorrect result. With no input current it drifts upwards slowly over 5 minutes. This situation will never happen in practice as I expect the rest of the circuit to draw >20uA at all times.

    So it appears a chopper-stabilised amplifier will work as an integrator.

    Kirill: I think your open loop simulation is correct on paper and looks even worse than my 1st amplifier. Before I commit to the design, there's a set of 20 test boards to make. I can measure the drift on these and get some idea of the spread.

    I never saw an op-amp circuit drift nearly so fast as the 1st one here. My circuit is an update of one which has much worse specs than the LTC2063 yet performs OK.

    The 4.7k can be reduced to further counteract the amplifer imperfections.

    Thanks for all your help and this was my first post in ADI Eng Zone since changing jobs. My new job has fewer restrictions on cost, so I can put in some more expensive parts from Analog!


  • Hi Rob,

    I think you should also try measuring offset voltage right on the board. This will give you the opportunity to find out the effect of the offset voltage on the circuit. This is interesting at least from a theoretical point of view.

    The 4.7k can be reduced to further counteract the amplifer imperfections

    That doesn't seem like a good idea to me. As you probably know, the integrator integrates the input current in the time domain and, ideally, should receive the input signal from a source with infinitely large internal resistance. Increasing the resistor would be preferable if the requirements of your design allow it.

    Wait for results.