I'm working on an integrator circuit, part of which is attached. Instead of a slow drift, the output ramps to Vcc in a minute or so. Also a significant voltage (200mV) is needed to arrest the drift.LTC2063 was used because of low offset voltage and low current <5uA. Perhaps zero drift op-amps are not suitable for this job? The LTSPICE result looks perfect though.I have a dev board type DC2837A with the core circuit shown in the attachment. I'm feeding it at points A/B for the input voltage. It takes 50x the expected input voltage to affect the drift. The current is from a 100k resistor and a 30V variable power supply, I = V/100k = 300uA max. The variable power supply is not outside the amplifier common mode or anything.Does anyone know if the LTC2063 is suitable for an integrator like this? Can anyone suggest a better part, bearing in mind it must be <5uA supply current?The rest of the circuit which resets the integrator is not shown, and not fitted yet. There's no point in building the rest until the basic integrator is working.
Could you clarify more about the inputs you've place on points A/B. Also, what do you mean about the 200mV needed to arrest the drift?
If I'm understanding you completely, you want to use the LTC2063 as an integrator that ramps up to VCC in about a minute?
To correct myself, it takes 200uV across the points A/B to stop the amplifier drifting towards Vcc. The voltage is applied by a 10V power supply and 100k resistor across A/B. This gives 2/10k x 10V = 200uV on the amplifier inputs.
The input offset of LTC2063 is specified as 10uV maximum. But it needs 20x the input offset to make the amplifier output change. That is surely not right?
I want the integrator output to remain constant (hold) if there is no input at all. Obviously the output will drift, but under 2 minutes to go hard over seems wrong.
I'm stripping down the DC2837A dev board today, replacing the parts and cleaning it. That will eliminate any doubts about the construction.
Why both inputs of op-amp are floating in your design? The rest of the circuit pulls the non-inverting input to some potential, as is customary in integrators?
The amplifier attempts to compensate for any differential voltage between the inputs via a feedback loop. In your case, it passes a constant current through the capacitor. If you can measure the slope of the output voltage, you can calculate current through the feedback capacitor. This will help to better understand the cause of your scheme's behavior.
The inputs are not floating, it's only shown that way to simplfy and avoid confusion! The inputs are mid-rail.
The slope is about 25mV/s. That works out to far more current than should be happening with this op-amp.
I stripped off all spare parts and cleaned the board with solvent. No difference. Some alternative amplifiers arrived today to be tested tomorrow.
It doesn't make sense that such a high performance amplifier performs so poorly in this circuit.
I think I've figured out why you're seeing these confusing outputs:
1) The output of an R-C op-amp integrator is actually -Vout, an inverted version of the desired rising Vout signal. If you don't put in any input, and don't invert the output either, you should be seeing a high signal because that's the opposite of 0 Vin. Up high is the resting condition of the integrator output with no input applied.
The (relatively) fast slope you're seeing there is the slew rate of the output rising to where it's supposed to be; I'm impressed it's 25mV/s because our stated spec is more like 3.
The reason your 200uV offset seems to bring it down from rail is because any input signal will pull the output signal down, inversely proportional to itself.
To address this, you need another stage after this one that will do the inverting to convert the -Vout back to the desired polarity of Vout. A simple inverting amplifier will work. However, the catch is that if you're using this inverter in a single-supply configuration, it needs to be offset to mid-rail so it can pull down successfully. Otherwise, it will bottom out halfway through.
2) Node B needs to be connected directly to GND. This is because this is the reference node for the integrator to pull against. As the inputs get bigger and bigger, the op-amp will work harder to push IN- down to match IN+, and in doing so, create a negative output proportional to the input. Thus, IN+ has to be tied directly to GND, not through a resistor, so the op-amp output can pull all the way down to the bottom. If there's a series resistor there, the voltage will not be able to go down to 0.
This is a situation in which the balance resistor at IN+ isn't needed, since the node will be hard tied to ground anyway.
I have attached a .zip file with an LTspice of the integrator I described plus the additional inverting output stage with offset. Please try this out and let me know what you think.
LTC2063 Integrator + Inv.zip