I created a lt spice model of my circuit which consists of an op amp in a unity gain voltage follower configuration which feeds a SAR ADC. I also included the flywheel circuit in front of the adc. There are two models, each one having a different op amp.
The one labeled "bad" uses a TI 4111 which isn't really designed to handle the capacitive load my circuit has. I originally designed with this op amp before I knew the capacitance values. Thus I made a second circuit that uses an op amp with unlimited capacitance drive.
Using the analog suggestion on how to measure phase margin I plotted the following.
Not sure how to interpret these, it seems that the tlv4111 has more phase margin than the analog ada4807 which seems backwards to me given the load circuit. Any suggestions?
TLV4111 model: drive.google.com/open?id=16f1DOy9MGa5eAqLpUB9AkA7d-5P2t6DK
TLV4111 ac analysis: drive.google.com/open?id=1yB7cSt02a8esAloV1XLMuPj0H3VwHI5K
ADA4807 AC analysis: drive.google.com/open?id=1XzN9bI2dqWq7XrIicgfRNYllvPiZDeZM
What is the reference on measuring phase margin that you used??
In real life, RR-input op amps will change drastically when getting within a few houndred millivolts of the rail.
Put a 0.5V source in series with the non-inverting input to lift the inputs off ground and repeat the measurement.
Also see AN-1516 at ti.com.
I used this: https://www.analog.com/en/education/education-library/videos/5579254320001.html
I'll read the TI data, give your method a shot and report back.
I forgot to mention. All gbw and PM specs and also Bode plot graphs are with inputs and
outputs at mid-supply.
harry, made the update but it doesn't seem to have made a lick of difference.... Did i miss something?