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ADA4254 GAIN_CALx Register Specification Procedure

Category: Datasheet/Specs
Product Number: ADA4254

Hello.

I have questions about ADA4254.

I am evaluating the ADA4254, but when I specify a read operation on the GAIN_CALx register (steps (1) to (7) below), GPIO3 goes low (error occurs) after several hundred microseconds.

Is the following procedure for specifying the GAIN_CALx register correct?
I want to know the cause of GPIO3 going low.

<GAIN_CALx Register Configuration Procedure>

(1) Set CS to Low
(2) Transmit 0x00 (Specifies writing to the GAIN_MUX register)
(3) Transmit 0x03(Gain error for G = 4 V/V × 1 V/V)
(4) Set CS to High
(5) Wait 10μs
(6) Set CS to Low
(7) Transmit 0x16 (Specifies reading the GAIN_CAL7 register)
(8) Receive the 8-bit value from the GAIN_CAL7 register
(9) Set CS to High

<ADA4254 Configuration Details>
・Set GPIO_DIR bit 3 to 1, bit 4 to 0
・Set SF_CFG (0x0C) bit 3 (FAULT_INT_OUT) to 1, bit 4 to 1
・Set bit 4 of SYNC_CFG (0x02) to 1, set bits [2:0] to 000 (÷1)
・Leave CRC at default

<Error Phenomenon Details>
Masking ANALOG_ERR (0x04) produces the same phenomenon.
Additionally, masking any of the following via DIGITAL_ERR (0x03) eliminates the phenomenon:
・Bit 3 of DIGITAL_ERR (SPI SCLK count error)
・Bit 4 of DIGITAL_ERR (SPI read/write error)

Best regards.

Edit Notes

Conditional Modification
[編集者:miky、編集時刻: 12 Nov 2025 日 2:22 AM 時 (GMT -5)]
  • Hi,

    Could you specify what you meant by "masking"? I would like to understand what errors were triggered in the analog and digital error addresses. Were there any other errors in the digital_err field aside from bit 3 and bit 4? 

    Could you also share your timing specifications? 

    Regards,

    Kristine

  • Hi,  .

    Thank you for replying.

    “Masking” means setting individual bits in the DIGITAL_ERR_DIS or ANALOG_ERR_DIS registers to 1 to disable error flags.
    We apologize, but we cannot provide the waveform. However, GPIO3 goes Low 400~500μs after step (7) below.

    (1) Set CS to Low
    (2) Transmit 0x00 (Specifies writing to the GAIN_MUX register)
    (3) Transmit 0x03
    (4) Set CS to High
    (5) Wait 10μs
    (6) Set CS to Low
    (7) Transmit 0x96 (Specifies reading the GAIN_CAL7 register) After 500μs, GPIO3 goes Low
    (8) Receive the 8-bit value from the GAIN_CAL7 register
    (9) Set CS to High


    When reading DIGITAL_ERR (0x03) this time, only MM_CRC_ERR (bit1) was set to 1, indicating an error.
    Additionally, setting MM_CRC_ERR_DIS (bit1) to 1 via DIGITAL_ERR_DIS (0x0B) resolved the issue where GPIO3 went Low.

    The internal CRC appears to operate on a 512us cycle.

    Could this be affecting the GPIO3 going Low?

    Best regards.

  • Hi miky,

    I tried a quick setup replicating the steps you provided but the error does not seem to appear on my side.

    When reading GAIN_CAL7, GPIO3 does not go low on my end.

    (SCLK - yellow, SDO - blue, GPIO3 - red)

    CRC is disabled by default so we can't really confirm that this causes MM_CRC_ERR.

    It would be helpful if you could share your timing diagrams/specs so we could take a closer look on what had occur. You can also email me at kristine.hoffman@analog.com for the files or connect with our field team if possible.

    Thanks and regards,

    Kristine

  • Hi,  .

    Thank you for your replying.


    I have sent the details via email. Could you please review them?

    Best regards.