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Input biasing for AD8421

Thread Summary

The user is designing a 100x gain preamplifier for ultrasonic piezoelectric transducers (30 kHz–300 kHz, 5 mVpp) with a focus on low power consumption and cost. They need advice on evaluating CMRR with source mismatch and selecting input bias resistor values. The transducer is modeled as a 12 nF capacitance and 10 ohm resistance, and the user is open to suggestions for different components or topologies.
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Category: Hardware
Product Number: AD8421

Hi,

I am designing a preamplifier with a gain of 100x to amplify signals coming from ultrasonic piezoelectric transducers. The transducer generates differential signals in the 30 kHz–300 kHz range, with an amplitude of about 5 mVpp. I am not sure about the common-mode voltage amplitude. The main constraint of the design is power consumption + cost, since the device will be battery powered.

The transducer can be modeled as a series capacitance of 12nF and a series resistance of 10 ohms. In my LTSPICE simulation, I also included cables model to evaluate the CMRR performance when mismatch occurs.

The preliminary results look reasonable, but I still have some questions:

  • how should I properly evaluate CMRR in the case of source mismatch (i.e different cables lenght or slightly different sensors)?

  • Regarding the input bias resistors: how do I choose their value? The datasheet only reference the high-pass cutoff when using capacitive coupling at the input. In other designs, i see that high-value resistors (e.g. 1Mohm) are used.

Here's a screenshot of my simulation. I'm open to all kind of suggestions, including different p/n or topologies.

Thank you,
V