On the ADA4254 the SPI low on SDO/SCK are as expected when driven by Spartan 7 FPGA with around 40KR internal pull-up. They approach GND well.
However, /CS doesn't go below 500mV. The datasheet spec is OK to 800mV ViL but would prefer more headroom and be able to pull-down < 500mV.
Is there a reason for this internal to the /CS structure on the ADA4254?
Why is it different to SDO/SCK etc?
What is suggested to achieve being able to pull-down to < 500mV on /CS?