On the ADA4254 the SPI low on SDO/SCK are as expected when driven by Spartan 7 FPGA with around 40KR internal pull-up. They approach GND well.
However, /CS doesn't go below 500mV. The datasheet spec is OK to 800mV ViL but would prefer more headroom and be able to pull-down < 500mV.
Is there a reason for this internal to the /CS structure on the ADA4254?
Why is it different to SDO/SCK etc?
What is suggested to achieve being able to pull-down to < 500mV on /CS?
Thank you for using the ADA4254 on your application.I would think that the /CS pin should only detect the signal you applied on its input level and see if the levels are on either the Vil or Vih range indicated on the datasheet.
Have you tried checking the output level of your Spartan 7 FPGA's pin when it's not connected to the ADA4254?The Vol of the spartan-7 fpga can reach 0.4V based on the datasheet. Can you confirm this voltage level and what output configuration used for the /CS pin? is it similar with the SCK?
Though, I'll try to check the architecture of the digital interface of the ADA4254.Thanks natural_inquisitve.