AD8429 gain switching

For a data acquisition frontend we need an instrumentation amplifier with wide bandwidth, low distortion, and low noise. We are considering the AD8429. The frontend needs to capture signals with +/-10V, 1V, and 100mV full-scale range, requiring to switch the AD8429 gain setting resistor.

PCB space contraints do not allow to use relays as switches, so we are considering analog switches as shown in CN0146. Unfortunately the suitable analog switches with low Rds_on and low delta-Rds do have large input and output capacitances (e.g. ADG1402: Cd_off = 41pF, Cs_off = 36pF). If such a switch is connected to the RG-terminals these capacitances become part of the feedback network and reduce the feedback for the higher frequencies, resulting in a frequency-dependent rise of gain. In case of the AD8429 simulation and calculation show an 18dB peak at ~9MHz for gain=1, and a 5dB peak at gain=10. We are afraid these peaks, esp. at gain=1, will cause problems with increased HF-noise, RFI immunity and stability. Since we cannot access the internal feedback resistors, we see no chance to compensate the parasitic capacitance of the analog switches.

We cannot use an instrumentation amp with lower GBW (which will "mask" the gain rise) because this would significantly increase distortion on higher input frequencies. Also the AD8253 with built-in gain switches is not a suitable alternative because of its higher input noise.

Has anyone encountered (and hopefully solved) a similar problem?

Many thanks, Bdolf

  • Hello Bdolf,

    You have pointed out many valid points. Instrumentation amplifiers like AD8429 don't lend themselves very well to build fast and precise PGIAs because of the problems you mention in your post, being the parasitics added to the RG pins one of the most problematic aspects. You can find more details here:

    If you feel that AD8253 is not suitable because of its input noise, have you considered rolling up your own PGIA? Do you have enough space on your board? You could do it with a small low-noise dual Op Amp (like AD8599 for precision or ADA4898-2 if you need faster but bigger) followed by difference amplifier like AD8271. The difference amplifier would give you excellent CMRR at low gains and save you the resistors for the subtractor. An advantage is that once you have access to the inputs of the Op Amps, you don't need to worry so much about the channel resistance because it does not show up in series with your gain resistors, and can increase it to minimize input capacitance. And then, of course, you can compensate it to avoid gain peaking or instability. Of course, you can increase complexity at the expense of cost and board area, but I gather you don't have much of the latter.

    Let me know what you think...



  • Hello Gustavo,

    many thanks for your suggestions! It seems we cannot avoid building our own PGIA. Splitting the gain resistors to isolate the parasitic switch capacitance as described in this thread ( helps a lot on higher gains, but is unfortunately almost useless at gain=1.

    The main problem with a "discrete" PGIA is to achieve good common mode rejection without manual adjustments. We do need gain switching in the input stage to achieve good SNR in the 1V and 100mV input ranges. However, even expensive matched resistor pairs will limit the CMR to 80dB at best, and require manual trimming to achieve the 100dB or more of an integrated instrumentation amp. Since the input sources will often be connected with long cables, good CMR is a must.

    Are there any other architectures besides the 3-op instrumentation amplifier, which could achieve our design goals: switchable gain 1x, 10, 100x, wide bandwidth (50kHz minimum at gain=100), and low noise (SNR >= 90dB at gain=100) ?



  • Harry,

    the circuit diagram of the AD8429 shows the RG-pins connected to the emitters of the input transistors, and the signal inputs connected to the bases. Since the signal inputs of the three AD8429 will be connected in parallel in your circuit, is the internal isolation between E and B of the input transistors sufficient to prevent any side effects caused by overloading the other op-amps stages? Assuming the inputs of a stage with gain=100 and a stage with gain=1 in parallel, driven by a 10V input signal: The x100 stage will be driven into saturation by the 10V input signal. According to my simulation, a half-wave rectified signal with 4V peak will appear on each RG terminal (emitter of the input transistor). I am afraid this will feed through the emitter-base junction and cause some ill effects in the input of the x1 gain stage.



  • Bdolf,

      Can you put three analog front ends in parallel and switch the outputs?  Yes, you will overload the

    100x and maybe the 10x, but depending on the part, the overload recovery time might not be too great.


  • Hi Bdolf,

    With regards to your comment:

    "However, even expensive matched resistor pairs will limit the CMR to 80dB at best, and require manual trimming to achieve the 100dB or more of an integrated instrumentation amp."

    This is absolutely true. We do this trimming ourselves inside the IC to get high common-mode rejection, but we do it in our diff-amps too. If you consider the AD8271, the resistors are already trimmed, and the B grade guarantees 80dB CMRR. I'm assuming you'll be using G=10 for your 1V range and G=100 for your 100mV range. Assuming perfect matching between the input amplifiers, you would get overall CMRR of 100dB for G=10 and 120dB for G=100. But because the first stage is not going to be perfect, you may not get there, but it is difficult to predict how high it is going to get. And you can't just base it off the CMRR spec on the Op Amps, but that Op Amp spec does correlate to overall CMRR. And if you look at AD8599, CMRR is guaranteed to be >115dB over temperature.

    As Harry has suggested, having different amplifiers for each gain can be an option, but I would like to point out something. In-Amps like AD8429 will increase their input current when the first stage is overloaded. Let's just take the G=100 and G=1 as example. You can have 10V across the G=1 (no RG) amplifier but the same will appear across the G=100 with RG=60. If you look at figure 46 on the AD8429's data sheet, you'll see that this voltage minus 2 diode drops will appear across RG, so we're talking about ~150mA flowing into one input and out of the other. If you had enough current from your source, this condition would damage the In-Amp; if you hadn't, it would clamp the input signal.

    So, what to do? You could add current-limiting resistors to protect the inputs of the high gain amplifier, but this would increase the noise for low signals, which goes against your wishes. You can add external clamping diodes as shown on page 17 in the data sheet, which lowers the noise, but not the input current (and can introduce errors due to leakage). You could buffer the inputs, which doesn't solve the noise problem, but you'll need to balance the linearity of the previous stage due to loading with the noise... or you can go for a more complicated current-limiting circuit per high gain channel...

    What you might be able to do is to mux the inputs into the appropriate amplifier and then de-mux them. As with any solution, you still have potential for overloading (wrong signal, wrong channel), but you don't have the high gain channel hurting your low gain channel at the same time, which allows another degree of freedom in your design.

    You will have to consider overloading conditions if you roll up your own PGIA too. In that case you have even more freedom to prevent/improve overload recovery but that is at the expense of complexity.

    I hope this helps.