AD8253 excessive bias current

Emman,

Thanks for the quick response. Attached is my application circuit. It is

a ruggedized 4-channel 1 MS/s 18-bit DAQ front end that supports

voltage, DC Bridge, thermocouple and IEPE inputs. I literally evaluated

every PGA on earth for this app and I am very happy with the size,

bandwidth, noise and precision. However I am seeing an unexpectedly

large offset voltage. For testing I have removed the clamp diodes D5/D6,

solid-state relays K1/K2, analog switches AK4, and shunt cal resistor

R129, leaving U32 inputs open. I added 1Mohm film resistors directly

from pin 1 to AGND and pin 10 to AGND to minimize the possibility of PCB

leakage. Thus the AD8253 U32 is presently seeing only 1Mohm from each

input to GND and a quarter-inch of open PCB trace. The filtered +/-7V

rails come from local LTC LTM8022 micromodules, are clean (few mV

wideband noise) and stiff. I am using a Gain of 1, although other gains

do not appear to change the observation. My BAL_P bias signal at the

AD8253 REF pin is a well-filtered 2.50V.

With no input signal on a number of samples, I measure with a Keithley

2001 DVM anywhere from +20 mV to +50 mV at the U32 AD8253 input pins 1

and 10. In the Keithley's 2-wire DC current mode measuring from input

pins to AGND, I measure a similar number of nanoamps, +20-ish to +50-ish

nanoamps, seemingly confirming the offset voltage is proportional to the

current times 1e6. Although the AD8253 datasheet specifies Ib and Ios of

5 nA typical, I find no cases in 12 samples where my in-circuit

measurement is less than 4-10x this number at room temperature.

In my AC-coupled IEPE mode where Zin is 1 Mohm, this offset causes a

baseline error higher than expected and I can't correct it by my usual

auto-zeroing technique of opening the signal path and grounding the

input pins momentarily before acquisition. That is the purpose of

K1/K2/AK4A/AK4D in the circuit, but it provides a low-Z to AGND and

shunts out the offset current/voltage. (If I instead shunted to AGND via

1 Mohm to match the IEPE case, it would be hugely wrong for other

coupling modes where the signal impedance is much smaller e.g. DC

bridge, thermocouple).

Although I normally use FET op amps for our Hi-Z front ends, this rugged

application is space and power constrained so I don't have the luxury.

Appreciate any suggestions. You folks have been very helpful in the past

when I've been in a bind.

Regards,

Gary

Emman,

Thanks for the quick response. Attached is my application circuit. It is

a ruggedized 4-channel 1 MS/s 18-bit DAQ front end that supports

voltage, DC Bridge, thermocouple and IEPE inputs. I literally evaluated

every PGA on earth for this app and I am very happy with the size,

bandwidth, noise and precision. However I am seeing an unexpectedly

large offset voltage. For testing I have removed the clamp diodes D5/D6,

solid-state relays K1/K2, analog switches AK4, and shunt cal resistor

R129, leaving U32 inputs open. I added 1Mohm film resistors directly

from pin 1 to AGND and pin 10 to AGND to minimize the possibility of PCB

leakage. Thus the AD8253 U32 is presently seeing only 1Mohm from each

input to GND and a quarter-inch of open PCB trace. The filtered +/-7V

rails come from local LTC LTM8022 micromodules, are clean (few mV

wideband noise) and stiff. I am using a Gain of 1, although other gains

do not appear to change the observation. My BAL_P bias signal at the

AD8253 REF pin is a well-filtered 2.50V.

With no input signal on a number of samples, I measure with a Keithley

2001 DVM anywhere from +20 mV to +50 mV at the U32 AD8253 input pins 1

and 10. In the Keithley's 2-wire DC current mode measuring from input

pins to AGND, I measure a similar number of nanoamps, +20-ish to +50-ish

nanoamps, seemingly confirming the offset voltage is proportional to the

current times 1e6. Although the AD8253 datasheet specifies Ib and Ios of

5 nA typical, I find no cases in 12 samples where my in-circuit

measurement is less than 4-10x this number at room temperature.

In my AC-coupled IEPE mode where Zin is 1 Mohm, this offset causes a

baseline error higher than expected and I can't correct it by my usual

auto-zeroing technique of opening the signal path and grounding the

input pins momentarily before acquisition. That is the purpose of

K1/K2/AK4A/AK4D in the circuit, but it provides a low-Z to AGND and

shunts out the offset current/voltage. (If I instead shunted to AGND via

1 Mohm to match the IEPE case, it would be hugely wrong for other

coupling modes where the signal impedance is much smaller e.g. DC

bridge, thermocouple).

Although I normally use FET op amps for our Hi-Z front ends, this rugged

application is space and power constrained so I don't have the luxury.

Appreciate any suggestions. You folks have been very helpful in the past

when I've been in a bind.

Regards,

Gary