AD8253 excessive bias current

Using AD8253 in classic scope-type DAQ front end. Both inputs have 1 Mohm to ground. In an AC-coupled mode, the amp Ib develops offset voltage across the input resistor. Data sheet specs indicate 5 nA typical, 50 nA max over temp, further supported by Figures 8, 9, 18 and 19. I am seeing consistent 30-50 nA = 30-50 mV on tens of samples with all my other circuitry isolated. Any hints?

  • 0
    •  Analog Employees 
    on Mar 13, 2017 3:49 PM

    Hi Gary,

    May I know how are you conducting your measurements?

    Are you using a precision voltmeter?

    At what nodes are you getting your measurements?

    What is the gain of the amplifier?

    If you could share your actual schematic here then it would be easier for us to troubleshoot your problem.

    Best regards,


  • Emman,

    Thanks for the quick response. Attached is my application circuit. It is

    a ruggedized 4-channel 1 MS/s 18-bit DAQ front end that supports

    voltage, DC Bridge, thermocouple and IEPE inputs. I literally evaluated

    every PGA on earth for this app and I am very happy with the size,

    bandwidth, noise and precision. However I am seeing an unexpectedly

    large offset voltage. For testing I have removed the clamp diodes D5/D6,

    solid-state relays K1/K2, analog switches AK4, and shunt cal resistor

    R129, leaving U32 inputs open. I added 1Mohm film resistors directly

    from pin 1 to AGND and pin 10 to AGND to minimize the possibility of PCB

    leakage. Thus the AD8253 U32 is presently seeing only 1Mohm from each

    input to GND and a quarter-inch of open PCB trace. The filtered +/-7V

    rails come from local LTC LTM8022 micromodules, are clean (few mV

    wideband noise) and stiff. I am using a Gain of 1, although other gains

    do not appear to change the observation. My BAL_P bias signal at the

    AD8253 REF pin is a well-filtered 2.50V.

    With no input signal on a number of samples, I measure with a Keithley

    2001 DVM anywhere from +20 mV to +50 mV at the U32 AD8253 input pins 1

    and 10. In the Keithley's 2-wire DC current mode measuring from input

    pins to AGND, I measure a similar number of nanoamps, +20-ish to +50-ish

    nanoamps, seemingly confirming the offset voltage is proportional to the

    current times 1e6. Although the AD8253 datasheet specifies Ib and Ios of

    5 nA typical, I find no cases in 12 samples where my in-circuit

    measurement is less than 4-10x this number at room temperature.

    In my AC-coupled IEPE mode where Zin is 1 Mohm, this offset causes a

    baseline error higher than expected and I can't correct it by my usual

    auto-zeroing technique of opening the signal path and grounding the

    input pins momentarily before acquisition. That is the purpose of

    K1/K2/AK4A/AK4D in the circuit, but it provides a low-Z to AGND and

    shunts out the offset current/voltage. (If I instead shunted to AGND via

    1 Mohm to match the IEPE case, it would be hugely wrong for other

    coupling modes where the signal impedance is much smaller e.g. DC

    bridge, thermocouple).

    Although I normally use FET op amps for our Hi-Z front ends, this rugged

    application is space and power constrained so I don't have the luxury.

    Appreciate any suggestions. You folks have been very helpful in the past

    when I've been in a bind.



  • Harry,

    Thank you for the immediate feedback. I'm fairly familiar with "typical"

    specs in a competitive world - in marketing terms it normally means we

    saw one almost this good once, but in engineering terms I have to depend

    on published specs to be somewhat useful for rough guidance. If I get

    worst case Ib at room temperature and if it increases by several times

    again over temperature as datasheet Fig. 19 implies, I could have an

    18-bit DAQ design with a 25% offset error spec. That's a problem for me,

    and would require a few days with a Tenney to find out.

    If a large customer is consuming binned parts we don't have the volume

    to compete with that. Is that a thought example or are you allowed to

    say if it's reality with this part?



  • Gary,

      What does "typical" mean?  Is it an average?  A mean?  An average plus one standard deviation?

    I've always considered "typical"s to be a waste of ink.  If it is an average, then 50% are higher

    and 50% are lower.  If a big guy pays for a special selection and sets his limit at typical, then

    ALL of the parts you get will be above typical.  For a worst case design, you have to use the max

    number, which is 50nA.


  • 0
    •  Analog Employees 
    on Mar 16, 2017 6:58 PM

    Hi Gary,

    For the AD8253, I would expect the distribution for Input Bias current to be the same for all customers.  Taking a look at your circuit, other than leaking from the diodes, or potentially leaving both AD8253s switched in, I suspect you are up against the input bias current for the part, with perhaps, another couple of nA due to input impedance.  One additional factor is that  the part is specified at +/-15V supplies, so by using +/-7V supplies, the inputs at 0V common mode are effectively closer to the rails giving another potential several nA as shown in figure 18 in the datasheet.

    Despite the parts being close to the edge of the distribution at room temperature, I would still expect the parts to maintain specifications of 60nA over the specified temperature range under datasheet conditions.

    It seems that when your are observing this effect, it is during an AC coupled measurement.  What is the target DC offset accuracy during this measurement?