ADA4254 Chopper Frequency Range

We are evaluating the ADA4254 as an AD7768 frontend. The datasheet recommends to synchronize the chopper frequency to the ADC master clock. The nominal chopper frequency is 1 MHz. The datasheet does not specify limits for the usable frequency range, however, the additional offset error caused by a chopper frequency deviation from the nominal value is specified:

Parameter: Differential Offset vs. External Clock Frequency, RTI - Test Condition 0.8 - 1.2 MHz

Does this implicate the chopper clock frequency must stay within 0.8 - 1.2 MHz limits? This would restrict the usable sampling frequency range of the AD7768: With the ADA4254 clock divider set to 16 the AD7768 MCLK must stay within 16.384 to 19.2 MHz, with clock divider 32, MCLK must be 25.6 to 32.768MHz to keep the chopper clock within limits. Sampling frequencies between 18.75 and 25 kSps (MCLK 192. to 35.6 MHz) cannot be used. Our requirement however is a continuous sampling frequency range from 16 to 32 kSps.

Must we add an external switchable pre-divider to keep the chopper clock inside the 0.8 to 1.2 MHz window, or does the ADA4254 allow a wider range? If the latter is true, what is the impact on offset errors?

Many thanks, AK

  • Sorry, corrected a typo:

    Sampling frequencies between 18.75 and 25 kSps (MCLK 19.2 to 25.6 MHz) cannot be used

  • Hi bdolf,

    Good day!
    Looking at the datasheet the frequency range of the clock frequency is in the spec table:

    You're right that the ADA4254's master clock should be in this range and therefore when applying an external clock, once it's divided within the ADA4254 it has to be in this range as this will derive the other clocks needed in the ADA4254.

    With regards to the AD7768, I had a quick look at the datasheet. Since you mentioned that your required sampling frequency is from 16 to 32kSps, what clock frequency do you plan to use on MCLK? I would have to check this in with the ADC guys for confirmation but with the right configuration the 32.768MHz or 16MHz clock can be set to have the sampling frequency on your desired spec.

    Thanks and I hope this helps bdolf.

    Best Regards,

  • Hi Dann,

    many thanks!

    Our application requires a gapless programmable sampling frequency from 16 to 32 kHz, so the AD7768 MCLK is anywhere between 16.384 and 32.768 MHz. We plan to use a switchable divider div2 / div3: Div 2 for MCLK from16.384 to 19.2 MHz. With the ADA4254 internal divider set to 8 this will result in a 1.024 to 1.2 MHz chopper clock. For MCLK 19.2 to 27.2 MHz we will switch the divider to div3, resulting in 0.8 to 1.133 MHz chopper clock. Finally for higher MCLK we will use div 2 and the ADA4254 divider set to 16, yielding 0.85 to 1.024 MHz chopper clock.

    The datasheet also mentions a requirement for a 50% duty cycle clock. Is this still valid if the ADA4254 internal clock divider is used? If yes we will need an additional D-flipflop because the div3 divider output has 33% duty cycle.

    Best Regards,