We are evaluating the ADA4254 as an AD7768 frontend. The datasheet recommends to synchronize the chopper frequency to the ADC master clock. The nominal chopper frequency is 1 MHz. The datasheet does not specify limits for the usable frequency range, however, the additional offset error caused by a chopper frequency deviation from the nominal value is specified:
Parameter: Differential Offset vs. External Clock Frequency, RTI - Test Condition 0.8 - 1.2 MHz
Does this implicate the chopper clock frequency must stay within 0.8 - 1.2 MHz limits? This would restrict the usable sampling frequency range of the AD7768: With the ADA4254 clock divider set to 16 the AD7768 MCLK must stay within 16.384 to 19.2 MHz, with clock divider 32, MCLK must be 25.6 to 32.768MHz to keep the chopper clock within limits. Sampling frequencies between 18.75 and 25 kSps (MCLK 192. to 35.6 MHz) cannot be used. Our requirement however is a continuous sampling frequency range from 16 to 32 kSps.
Must we add an external switchable pre-divider to keep the chopper clock inside the 0.8 to 1.2 MHz window, or does the ADA4254 allow a wider range? If the latter is true, what is the impact on offset errors?
Many thanks, AK