1) Kindly provide any other opamp having higher CMRR, but with similar specification of ADA4895.
2) Kindly provide methods to improve CMRR of opamp apart from resistor matching.
1) Kindly provide any other opamp having higher CMRR, but with similar specification of ADA4895.
2) Kindly provide methods to improve CMRR of opamp apart from resistor matching.
Hi rmurthy720,
The guaranteed DC CMRR of 100dB for ADA4895 is hard to beat for most high frequency devices I searched for. However, I've shown a list of comparable ADI devices you could look through:
| Part # | Feedback Type | CMRR (min) | Temp Range | # of Amps | GBP (typ) | Slew Rate (typ) | Vos (max) | VNoise Density (typ) | Ibias (max) | Iq/Amp (typ) | Vs span (min) | Vs span (max) | Price (1000+) | Associated Model | Package Area |
| (dB) | (Hz) | (V/us) | (V) | (V/rtHz) | (A) | (A) | (V) | (V) | ($ US) | (mm²) | |||||
| LTC6229 | Voltage | 100 | -40 to 125°C | 2 | 890M | 500 | 95µ | 880p | 2.5µ | 16m | 2.8 | 11.75 | $2.37 | (LTC6229IDD#PBF) | 9mm² (10-Lead DFN (3mm x 3mm w/ EP)) (LTC6229HDD#PBF) |
| LTC6228 | Voltage | 100 | -40 to 125°C | 1 | 890M | 500 | 95µ | 880p | 2.5µ | 16m | 2.8 | 11.75 | $1.58 | (LTC6228IDC#TRPBF) | 4mm² (6-Lead DFN (2mm x 2mm w/ EP)) (LTC6228HDC#TRPBF) |
| LT1222 | Voltage | 100 | -40 to 85°C | 1 | 500M | 200 | 300µ | 3n | 300n | 8m | 5 | 36 | $4.25 | (LT1222CN8#PBF) | 31.00979mm² (8-Lead SOIC (Narrow 0.15 Inch)) (LT1222CS8#PBF) |
| ADA4895-2 | Voltage | 100 | -40 to 125°C | 2 | 1.5G | 943 | 350µ | 1n | 16µ | 3m | 3 | 10 | $3.21 | (ADA4895-2ARMZ) | 15.965mm² (10-Lead MSOP) (ADA4895-2ARMZ) |
| ADA4895-1 | Voltage | 100 | -40 to 125°C | 1 | 1.5G | 943 | 350µ | 1n | 16µ | 3m | 3 | 10 | $1.89 | (ADA4895-1ARJZ-R7) | 9mm² (6-Lead SOT-23) (ADA4895-1ARJZ-R7) |
| AD829 | Voltage | 100 | -55 to 125°C | 1 | 750M | 230 | 1m | 1.7n | 7µ | 5.3m | 9 | 36 | $3.65 | (AD829ARZ) | 31mm² (8-Lead SOIC) (AD829JRZ-REEL) |
| AD8099 | Voltage | 98 | -40 to 125°C | 1 | 3.8G | 470 | 500µ | 950p | 13µ | 15m | 5 | 12 | $2.00 | (AD8099ACPZ-REEL) | 9mm² (8-Lead LFCSP (3mm x 3mm w/ EP)) (AD8099ACPZ-REEL7) |
| LT6230-10 | Voltage | 95 | -40 to 85°C | 1 | 1.45G | 250 | 500µ | 1.1n | 10µ | 3.3m | 3 | 12.6 | $1.50 | (LT6230CS6-10#TRPBF) | 8.12mm² (6-Lead TSOT-23) (LT6230CS6-10#TRMPBF) |
| LT1226 | Voltage | 94 | 0 to 70°C | 1 | 1G | 400 | 1m | 2.6n | 8µ | 7m | 5 | 36 | $3.28 | (LT1226CN8#PBF) | 31.00979mm² (8-Lead SOIC (Narrow 0.15 Inch)) (LT1226CS8#PBF) |
| AD8021 | Voltage | 86 | -40 to 85°C | 1 | 1G | 130 | 1m | 2.1n | 11.3µ | 7.8m | 4.5 | 24 | $1.31 | (AD8021ARMZ) | 31mm² (8-Lead SOIC) (AD8021ARZ-REEL7) |
| LTC6254 | Voltage | 85 | -40 to 125°C | 4 | 720M | 280 | 350µ | 2.75n | 3µ | 3.3m | 2.5 | 5.25 | $3.55 | (LTC6254CMS#PBF) | 19.7911mm² (16-Lead MSOP) (LTC6254CMS#TRPBF) |
To improve CMRR: If there is anything that can be done to reduce the CM voltage variation that the device experiences, that would of course reduce the error voltage.
Also, I've not tested this but if you were to introduce a diff pair in front of an Op Amp (in a composite amplifier configuration), and used precision / tracking / matched resistors) this would boost the differential gain and should reduce CMRR. However, something tells me that you give up many things (e.g. offset error, bandwidth, noise, etc.) when you do something like this as a penalty. So, I'm not sure how practical this approach may be, but thought I mention it anyway.
Regards,
Hooman
Hi rmurthy720,
The guaranteed DC CMRR of 100dB for ADA4895 is hard to beat for most high frequency devices I searched for. However, I've shown a list of comparable ADI devices you could look through:
| Part # | Feedback Type | CMRR (min) | Temp Range | # of Amps | GBP (typ) | Slew Rate (typ) | Vos (max) | VNoise Density (typ) | Ibias (max) | Iq/Amp (typ) | Vs span (min) | Vs span (max) | Price (1000+) | Associated Model | Package Area |
| (dB) | (Hz) | (V/us) | (V) | (V/rtHz) | (A) | (A) | (V) | (V) | ($ US) | (mm²) | |||||
| LTC6229 | Voltage | 100 | -40 to 125°C | 2 | 890M | 500 | 95µ | 880p | 2.5µ | 16m | 2.8 | 11.75 | $2.37 | (LTC6229IDD#PBF) | 9mm² (10-Lead DFN (3mm x 3mm w/ EP)) (LTC6229HDD#PBF) |
| LTC6228 | Voltage | 100 | -40 to 125°C | 1 | 890M | 500 | 95µ | 880p | 2.5µ | 16m | 2.8 | 11.75 | $1.58 | (LTC6228IDC#TRPBF) | 4mm² (6-Lead DFN (2mm x 2mm w/ EP)) (LTC6228HDC#TRPBF) |
| LT1222 | Voltage | 100 | -40 to 85°C | 1 | 500M | 200 | 300µ | 3n | 300n | 8m | 5 | 36 | $4.25 | (LT1222CN8#PBF) | 31.00979mm² (8-Lead SOIC (Narrow 0.15 Inch)) (LT1222CS8#PBF) |
| ADA4895-2 | Voltage | 100 | -40 to 125°C | 2 | 1.5G | 943 | 350µ | 1n | 16µ | 3m | 3 | 10 | $3.21 | (ADA4895-2ARMZ) | 15.965mm² (10-Lead MSOP) (ADA4895-2ARMZ) |
| ADA4895-1 | Voltage | 100 | -40 to 125°C | 1 | 1.5G | 943 | 350µ | 1n | 16µ | 3m | 3 | 10 | $1.89 | (ADA4895-1ARJZ-R7) | 9mm² (6-Lead SOT-23) (ADA4895-1ARJZ-R7) |
| AD829 | Voltage | 100 | -55 to 125°C | 1 | 750M | 230 | 1m | 1.7n | 7µ | 5.3m | 9 | 36 | $3.65 | (AD829ARZ) | 31mm² (8-Lead SOIC) (AD829JRZ-REEL) |
| AD8099 | Voltage | 98 | -40 to 125°C | 1 | 3.8G | 470 | 500µ | 950p | 13µ | 15m | 5 | 12 | $2.00 | (AD8099ACPZ-REEL) | 9mm² (8-Lead LFCSP (3mm x 3mm w/ EP)) (AD8099ACPZ-REEL7) |
| LT6230-10 | Voltage | 95 | -40 to 85°C | 1 | 1.45G | 250 | 500µ | 1.1n | 10µ | 3.3m | 3 | 12.6 | $1.50 | (LT6230CS6-10#TRPBF) | 8.12mm² (6-Lead TSOT-23) (LT6230CS6-10#TRMPBF) |
| LT1226 | Voltage | 94 | 0 to 70°C | 1 | 1G | 400 | 1m | 2.6n | 8µ | 7m | 5 | 36 | $3.28 | (LT1226CN8#PBF) | 31.00979mm² (8-Lead SOIC (Narrow 0.15 Inch)) (LT1226CS8#PBF) |
| AD8021 | Voltage | 86 | -40 to 85°C | 1 | 1G | 130 | 1m | 2.1n | 11.3µ | 7.8m | 4.5 | 24 | $1.31 | (AD8021ARMZ) | 31mm² (8-Lead SOIC) (AD8021ARZ-REEL7) |
| LTC6254 | Voltage | 85 | -40 to 125°C | 4 | 720M | 280 | 350µ | 2.75n | 3µ | 3.3m | 2.5 | 5.25 | $3.55 | (LTC6254CMS#PBF) | 19.7911mm² (16-Lead MSOP) (LTC6254CMS#TRPBF) |
To improve CMRR: If there is anything that can be done to reduce the CM voltage variation that the device experiences, that would of course reduce the error voltage.
Also, I've not tested this but if you were to introduce a diff pair in front of an Op Amp (in a composite amplifier configuration), and used precision / tracking / matched resistors) this would boost the differential gain and should reduce CMRR. However, something tells me that you give up many things (e.g. offset error, bandwidth, noise, etc.) when you do something like this as a penalty. So, I'm not sure how practical this approach may be, but thought I mention it anyway.
Regards,
Hooman
Also, here is an article which may also help:
Regards,
Hooman
