Post Go back to editing

# ADA4625-1 LTspice Model Offset Voltage

Hello,

when simulating ADA4625-1 configured as simple unity gain buffer in LTspice with single 5V supply (Vs- =0, Vs+=5V), I get a systematic DC offset of -45.406mV which is far beyond the max value in the datasheet (+/- 1mV max). Is there a problem with the (LT)Spice model?

Thank you

Francois Dorel

Parents
• Hi Francois,

Try simulating the ADA4625-1 unity gain buffer with dual supplies instead. With a single supply, with input tied to ground, the output won't be able to swing all the way to ground and shows up as an offset at the output. Here you see the output is only 33nV:

Regards,

Hooman

• Hi Hooman,

from your example, I could figure out that the offset I have is not linked to single versus dual supply, but rather to the supply level which I used : 5V or +/- 2.5V on my side versus +/- 7.5V in your case. I reproduced your schematic and indeed got 33.3 nV offset at +/-7.5V supply.

My goal however is to used the ADA4625 at +/-2.5V (actually 0 - 5 V), which is OK based on datasheet. In this case I get -45.4 mV offset.

I swept the supply from +/-2.5 to +/-7.5V (symmetrically) and got the values of offset in the table below. You can see that offset goes from -45.4mV @ 5V supply (actually +/- 2.5V) to -83 nV when supply reaches 7V (+/- 3.5V). I have same results whether I use single or dual supply, since in any case I have the input of my unity gain buffer (opamp in+) at half supply (=ground in case of dual supply). The most important point for me is to know that I can rely on a maximum offset < 1mV as per the datasheet for 5V (single) supply, provided input common mode is around half supply. So, I would be reassured if we could conclude that the Spice model deviates from the reality at low supply voltages.

Regards
Francois

 Vs offset V(out) +/- 2.5V -45.4 mV +/- 3V -26 mV +/- 3.25V -15.4 mV +/- 3.3V -13.7 mV +/- 3.35V -10.6 mV +/- 3.4V -0.78 mV +/- 3.45V -0.0052 mV +/- 3.5V -83 nV
• P.S. : since datasheet specifies 5V to 36V single supply operation, another important point for me is to know if significant degradation of some performances, like offset, can be expected if supply is e.g. 3% below 5V. The only mention of a supply lower than 5V in datasheet in on page 5, where PSRR is specified for Vs = 4.5V to 10V (also figure 82 shows supply current versus Vs supply voltage).
Thank you

• Hi Francois,

I see the apparent simulated offset voltage increase you've reported as well when I change to +/-2.5V operation! I've asked people more familiar with the LTspice of ADA4625-1 and I'll get back to you when I hear from them.

Regards,

Hooman

• Hi Francois,

I've now heard back from the folks who maintain the LTspice models that the ADA4625-1 model has some issues when the supply voltage falls to less than +/-3.5V! They will be looking at updating the model to fix this issue. I don't yet have a time-line for when this task would be completed.

Thanks for bringing this to our attention and apologize for the inconvenience.

Regards,

Hooman

• Hi Francois,

I just noticed that you and I both may have been misled somehow on "Low supply" voltage operation. Keep in mind that the input Voltage range requires 3.5V headroom to V+. If you look at 5V operation table (datasheet page 5), you'll notice that the highest input voltage is 1.5V with 5V single supply (3.5V headroom). When you observe this limitation, the simulated output offset voltage is in the uV range which is correct.

So, I'd like to confirm with you that you also agree that it's the input voltage range condition that may have caused us to doubt the model. For now, I'll retract my comment about the model having issues at low supply voltage and instead attest that the model does not seem to have this offset issue we originally thought it does.

In this simulation, I've shifted the V+ and V- supplies such that there is 4V headroom from the input CM voltage to the V+ supply, and you can see that the output is very near 0V:

ADA4625-1 dual supply buffer Vs=+-2p5V 7_7_21.asc

Regards,

Hooman

• Hi Francois,

I just noticed that you and I both may have been misled somehow on "Low supply" voltage operation. Keep in mind that the input Voltage range requires 3.5V headroom to V+. If you look at 5V operation table (datasheet page 5), you'll notice that the highest input voltage is 1.5V with 5V single supply (3.5V headroom). When you observe this limitation, the simulated output offset voltage is in the uV range which is correct.

So, I'd like to confirm with you that you also agree that it's the input voltage range condition that may have caused us to doubt the model. For now, I'll retract my comment about the model having issues at low supply voltage and instead attest that the model does not seem to have this offset issue we originally thought it does.

In this simulation, I've shifted the V+ and V- supplies such that there is 4V headroom from the input CM voltage to the V+ supply, and you can see that the output is very near 0V:

ADA4625-1 dual supply buffer Vs=+-2p5V 7_7_21.asc

Regards,

Hooman

Children
• Hi Hooman,

I confirm that input CM headroom of less then 3.5V to V+ supply causes the offset to increase significantly. I have 875 nV for a marginal headroom of 3.5V that goes to 45mV when reducing headroom to 3V.

I'd really like to thank you for bringing this to my attention as I did not pay attention to this spec of input CM! And thanks to LTspice simulation.

best regards

François