ADA4895 Ground Plane - Reducing Stay Capacitance at Input and Output Pins

The ADA4985 datasheet says "It is important to avoid ground in the areas under and around the input and output of the ADA4895."  

Later it mentions how to connect the bypass caps to the ground plane.

I am unclear where there should be ground plane and where it should be void.  I do not see a void in the plane on the UG-112 and UG-838 op amp eval boards.  

Should I void the ground under power and ground pins and under the traces that go to them?

  • 0
    •  Analog Employees 
    on Apr 12, 2021 2:01 PM


    For optimal performance of the part, we should follow the data sheet as guide.
    I can see that the part was released later than the evaluation board and unfortunately, the Universal EVB doesn't have void on GND plane under the input and output pins.

    Are you planning to build your own board?
    The linked UGs were for SC-70 and SOT-23 parts, both are single channel where as your example picture is dual one.

    Thanks and regards!

  • I am using the dual-part device, but I would be open to using two of the single-channel version.

    I am confused by the Layout Considerations section.  

    • Input - Stay capacitance to ground lowers phase margin.
    • Output - Stay capacitance to ground creates a pole in the feedback loop

    Here is an example circuit shown in Figure 52 of the ADA4895 datasheet.  Non-inverting input, inverting input, and the output are purple, green, and blue respectively.

    I know the planes need to go close to the power pins, because the Layout Considerations section says bypass caps need to be as close to the part's power pins as possible and connect directly to the ground plane.  

    Do I need to void the planes under the purple, green, and blue areas?  If so, where do the high-speed return currents flow?  

    Thanks for helping me with this.  

  • Here is my layout, using the same color scheme as my last post.

    (If you need to download the image above, click here.)

    You can see where the signal, which is 100mV pulses of 15ns duration come in through a coax connector on the bottom left.  I I thought perhaps the return currents (yellow) will flow through the input load resistor.  I have voiced out the input, output, and FB path under the first and second stages.  The straight blue line represents a trace on the bottom side of the board.  

    The gray plane with voids is the ground plane on layer 2.  There is a power plane on layer 3, which I could void out in the same places as on layer 2.  

    As I write this I realize I need to expand the void on the right side so that it covers that output of Stage 1.  

    Is this approach right?  Does the benefit of reduced capacitance outweigh the cost of a cut up ground plane?  I have only voided the plane out under the inputs and outputs near the part, not all the way to the source driving the input and the load driven by this part's output.  Is this right?  

  • +1
    •  Analog Employees 
    on Apr 13, 2021 8:45 AM in reply to cgervasi


    You can void GND plane under the input and output pin.
    The stray capacitance introduced by the GND plane at the input will be added to the op-amp's input capacitance. Thus, will lower the phase margin and cause instability.
    The stray capacitance introduced by the GND plane at the output, is equivalent to capacitive loading, this creates a pole in the feedback loop. This can reduce the phase margin and the circuit may become unstable.

    Please try to check this article that may help you in designing high speed PCB.

    Thanks and regards!