ADCMP572 input signal pulse width issue

Hi Analog Support Team,

 

I have a question about ADCMP572 input signal pulse width.

Per datasheet, it says 80ps minimum pulse width.

Does it mean the comparator do not response to a input signal with a pulse less than 80ps?

 

In the latch signal description, latch setup time is 15ps and hold time is 5ps.

It describes the input signal should present 15ps before the latching threshold and keep it stable for at least 5ps after that.

It looks like ADCMP572 needs the input signal to be kept at least 20ps, not 80ps.

 

I felt very confuse about these 80ps term and 15ps / 5ps term.

Could you let me know if I misunderstood anything?

 

I am design a sampling circuit to catch a 30ps pulse with a ultra-fast comparator.

Not sure if ADCMP572 or any other Analog comparator could work on this.

Could you recommend any design to capture a 30ps pulse with either any comparator or very high speed sample-hold circuit?

Best Regards,

York

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  • 0
    •  Analog Employees 
    on Oct 6, 2020 10:53 AM 3 months ago

    Hi,

    Per datasheet, it says 80ps minimum pulse width.

    Does it mean the comparator do not response to a input signal with a pulse less than 80ps?

    Yes, because the output rise and fall times add to 70ps (35ps+35ps) and therefore any input pulse width less than 70ps will not appear at the output (refer to Figure 14 eye diagram).

    The figure 29 timing specifications are a guide to the latch to output timing (not for a minimum pulse width specification).

    Could you recommend any design to capture a 30ps pulse with either any comparator or very high speed sample-hold circuit?

    Not any comparator in the Analog Devices catalog or any competitive comparator that I know.

Reply
  • 0
    •  Analog Employees 
    on Oct 6, 2020 10:53 AM 3 months ago

    Hi,

    Per datasheet, it says 80ps minimum pulse width.

    Does it mean the comparator do not response to a input signal with a pulse less than 80ps?

    Yes, because the output rise and fall times add to 70ps (35ps+35ps) and therefore any input pulse width less than 70ps will not appear at the output (refer to Figure 14 eye diagram).

    The figure 29 timing specifications are a guide to the latch to output timing (not for a minimum pulse width specification).

    Could you recommend any design to capture a 30ps pulse with either any comparator or very high speed sample-hold circuit?

    Not any comparator in the Analog Devices catalog or any competitive comparator that I know.

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