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AD8450 with 42V battery


I am looking forward to using the AD8450 with batteries up to 42V. The Bus voltage would be 48V. Within specs from what I understand.

The 42V with the lowest PGDA gain (0.2) will lead to a worst case loop error of 8.4V, which is over the control voltage range for the ADP1974 I intend to connect to the VCTRL pin as in the application note/reference design.

I see two ways to deal with the problem:

1 -  add 400k worth of resistor in the PGDA input ladder in order to get a gain of 0.1 V/V. Would use 0.1%, 10ppm to 25ppm resistors.

2 - scale the output of the PGDA (BVMEA) by factor of 0.5 with divider opamp, set PGDA gain to 0.2 V/V.

Any of these lead to less bandwidth, more noise and possible loop stability issues...

I would appreciate feedback on these or other recommended solutions.

Kind regards,


  • Hi,

    There is a discussion about VINT Amplifier on page 26 of the data sheet.
    This Amplifier is also a clamp amplifier that drives the VCNTRL pin.
    This VCNTRL pin is the output of the AD8450 and the control input of the power converter.
    The output of the VINT amplifier is bounded by clamp voltages at VCLP and VCLN pins such that;

    VVCLN − 0.5 V < VVCTRL < VVCLP + 0.5 V.

    However, from the spec table,  Voltage Sense PGDA section, the maximum differential voltage is 29V only.
    This is with the test condition of AVCC = 25V and AVEE = -5V.
    The rated absolute maximum value for AVCC − AVEE is 36V, and the minimum operating AVCC and AVEE voltages are +5V
    and −5V, respectively.

    Thanks and regards.