Dear Analog Designers,
I have designed a compact PD amplifier for scientific research purposes which has the second stage shown in the attached schematics.
- Power supply is 3.3V to 0V.
- The input signal before C5 is 1.65V biased and MAX 2 x 37.5mV wide.
I want to bias the output of my second stage at 1.65V too, so I placed the network composed by R7/R8/C7, which produce c.ca 37.5mV DC at the non-inverting input. In this way, considering that the gain is set to 44, I would have the right DC biasing value at the output.
I did all the simulation with the real model in LTSpice and everything works like a charm.
But unfortunately this is not the case in the real prototype. I started checking the output bias voltage at it is only about 200mV. So I checked the non-inverting pin voltage and it is 37.9mV, fine.
Thus measuring the voltage from the non-inverting input to the inverting one I have 32.9mV, which is an hundred more than the expected input bias declared in the data sheet. So I though that I'm not working in the proper amplifier input range, maybe too close to the lower supply. I checked in the data sheet and this is not the case, because the inputs can go from the negative supply to V+ - 0.5V.
Applying positive short pulses at the input signal it works fine but I don't really like to lose all the other range.
Have you any ideas about what could be wrong in this circuit?
Thank for your kind support in advance
Cheers
Francesco
