LTC6268-10 input offset higher than specified?

Dear Analog Designers,

I have designed a compact PD amplifier for scientific research purposes which has the second stage shown in the attached schematics.

- Power supply is 3.3V to 0V.

- The input signal before C5 is 1.65V biased and MAX 2 x 37.5mV wide.

I want to bias the output of my second stage at 1.65V too, so I placed the network composed by R7/R8/C7, which produce c.ca 37.5mV DC at the non-inverting input. In this way, considering that the gain is set to 44, I would have the right DC biasing value at the output.

I did all the simulation with the real model in LTSpice and everything works like a charm.

But unfortunately this is not the case in the real prototype. I started checking the output bias voltage at it is only about 200mV. So I checked the non-inverting pin voltage and it is 37.9mV, fine.

Thus measuring the voltage from the non-inverting input to the inverting one I have 32.9mV, which is an hundred more than the expected input bias declared in the data sheet. So I though that I'm not working in the proper amplifier input range, maybe too close to the lower supply. I checked in the data sheet and this is not the case, because the inputs can go from the negative supply to V+ - 0.5V.

Applying positive short pulses at the input signal it works fine but I don't really like to lose all the other range.

Have you any ideas about what could be wrong in this circuit?

Thank for your kind support in advance

Cheers

Francesco

 

Parents
  • I sent an email to the AD technical support with all simulations etc, I'm attaching the simulation here too with results.

    I have changed a bit my mind. I don't think that the issue is related to the input bias, but to a not proper linear working region. It looks like a common mode of about 37.5mV at the input it is too close to the negative rail (GND). I bet that it would work with a dual supply.

    However in my datasheet "interpretation" it seems that inputs can go down to GND to VCC-0.5V.

    --Simulation code on LTSPICE

    ********************************************

    ** Second Stage Amplifier

    ** Francesco Martina 2020

    ********************************************

    *XU1 p n out vcc vdd s LTC6268-10

    *opamp and feedback

    X2 inp inn out vp vn vp LTC6268-10

    R10 inn 0 1k

    R9 out inn 43k

    *HP fcut ~ 60kHz

    R4 inp bias 100k

    C5 in inp 27p

    R7 bias vp 10k

    R8 bias vn 115

    C7 bias 0 10u

    *input signal

    VCP in 0 DC 1.65 PULSE(0 10m 0 100p 100p 10n 200n) AC 10m 0

    *out

    Cout out outac 5.6n

    Rl outac 0 499

    *Supply

    V1 vp 0 3.3

    V2 0 vn 0

    .lib LTC2.lib

    .backanno

    *.AC DEC 200 10 10G

    .TRAN 100p 0.5u

    .end

Reply
  • I sent an email to the AD technical support with all simulations etc, I'm attaching the simulation here too with results.

    I have changed a bit my mind. I don't think that the issue is related to the input bias, but to a not proper linear working region. It looks like a common mode of about 37.5mV at the input it is too close to the negative rail (GND). I bet that it would work with a dual supply.

    However in my datasheet "interpretation" it seems that inputs can go down to GND to VCC-0.5V.

    --Simulation code on LTSPICE

    ********************************************

    ** Second Stage Amplifier

    ** Francesco Martina 2020

    ********************************************

    *XU1 p n out vcc vdd s LTC6268-10

    *opamp and feedback

    X2 inp inn out vp vn vp LTC6268-10

    R10 inn 0 1k

    R9 out inn 43k

    *HP fcut ~ 60kHz

    R4 inp bias 100k

    C5 in inp 27p

    R7 bias vp 10k

    R8 bias vn 115

    C7 bias 0 10u

    *input signal

    VCP in 0 DC 1.65 PULSE(0 10m 0 100p 100p 10n 200n) AC 10m 0

    *out

    Cout out outac 5.6n

    Rl outac 0 499

    *Supply

    V1 vp 0 3.3

    V2 0 vn 0

    .lib LTC2.lib

    .backanno

    *.AC DEC 200 10 10G

    .TRAN 100p 0.5u

    .end

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