Transimpedance Amplifier (Photodiode interface)

Hello All,

I have been dropped into a design that has seen several other engineers before me.  The goals are common make it good, cheap and low power.  My goal however is just to make it work well.  I think the other aspects can gain perspective from that starting point.

The design as it was when I was placed on the project does not function well but in its defense the signal we are trying to detect is quite low.

There are three stages in the existing design.

STAGE 1: transimpedance amplifier that uses a JFET front end.  The feed back resistor and capacitor are 50M and 1pF respectively.  This seems fairly common for the application but I am unsure how it effects the gain of a standard transimpedance amp

STAGE 2/3:  Are identical gain stage integrators each set to a gain of 75! with input RC networks of the same time constant as the feedback network on the stage preceding it.

Functional Description:  The input source is a scintillator tube that converts gamma radiation into photons which then excite the photodiode which creates about 10,000 electron/hole pairs which the transimpedance amp converts to a voltage spike.  The following stages gain that spike and integrate it to appear more like a Gaussian pulse.

I don't know my way around op amps well enough to decide which minute details are going to fix or destroy the performance.  That is where I hope to gain some insight from you.

Here is what I do know: 

(1) The based on the radiation energy, the crystal light yield and the optical coupling efficiency I can say that the largest charge I expect to see at the input is 1.74 x10-15 Coulombs.

(2) I have read that the photodiode capacitance should match the JFET input capacitance which are 20pF and 10pF respectively.

(3) Increasing the Feedback resistor should improve the gain, but at what cost.  Also I am unsure what the gain is for the first stage.

Here is what I fear:

(1) That I am not optimized at the first stage which is leading to bad SNR and requiring too much gain in later stages.

(2) Gain of 75 on stages 2 and 3 is narrowing the bandwidth of the amp to the point where it is not truly able to amplify the signal by 75.

Is Anybody out there familiar with this type of circuit?

Thanks for reading.

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  • Rookie,

      When I do a sim on the power supply, you have no attenuation with R20 and C20 until you get past

    15 kHz.  Try increasing R20 to 100 ohms and C20 to 10 uF.  Would also help to put a small ceramic

    (0.001-0.01uF) across C20.

    The AD8541 is CMOS.  Did you mean AD8641 or AD8642?

    Have you actually measured the reference design or do someone say it works?

    What is trip point?  Is this V1 on your schematic?

    WRT "my ratio of detected events to ambient has climbed from 1.4:1 to 2.1:1!"  Is this good or bad??

    Bad because you are seeing noise?

    Harry

Reply
  • Rookie,

      When I do a sim on the power supply, you have no attenuation with R20 and C20 until you get past

    15 kHz.  Try increasing R20 to 100 ohms and C20 to 10 uF.  Would also help to put a small ceramic

    (0.001-0.01uF) across C20.

    The AD8541 is CMOS.  Did you mean AD8641 or AD8642?

    Have you actually measured the reference design or do someone say it works?

    What is trip point?  Is this V1 on your schematic?

    WRT "my ratio of detected events to ambient has climbed from 1.4:1 to 2.1:1!"  Is this good or bad??

    Bad because you are seeing noise?

    Harry

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