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Self Latching Comparator

Hello,

I'm trying to use the ADCMP553 comparator to capture and hold a fast trigger signal. I would like to somehow feedback the output of the comparator to the latch so that when the comparator goes HIGH it stays high. I would use a signal from an FPGA to reset the latch. Has anyone done something like this or is there any app note somewhere?

I've attached a schematic of one way I could imagine doing this except that the latch signals are not LVPECL compliant. (Also it is just half of the differential pair.) In this scheme, the Trigger Reset pin would be tri-stated until the trigger was read into the FPGA. At this point, the Trigger Reset pin would be pulled Low (or High depending on which half of the differential pair it was connected to) to reset the comparator to compare mode.

Thanks for any help or ideas,

-Schuyler

  • Hi, ShuylerSG.

    I'm looking into this. I'll get back to you soon.

    Regards,

    Anna

  • Thanks - I look forward to any ideas you have. -Schuyler

  • Hi Anna,

    Any luck with ideas for the self latching comparator?

    -Schuyler

  • Hi, Schuyler.

     

    I have ideas on your application but I’m still confirming it. Anyway, I think your application is possible but there are things to consider.

    1.       1.The Latch Enable Pin function in the datasheet is active LOW, so when the Q output goes high, the Latch pin receives a high signal as well, and it will still go to compare mode. I think one concern to look at could be the default level of the output during power-up, if by default the output is pulled down to ground, then I would think that by default, the part is in LATCH MODE, then this means the output won’t change and remains LOW even if you crank the non-inverting input. With this, you have to know the conditions during power-up. Another is to consider using Qbar instead.

    2.        2.The Latch Enable Pin should be a PECL value or should follow the datasheet’s specifications under Latch Enable Characteristics table, page 3, in order to have the expected performance of the part.

    3.        3.Since you are using only LEA, I think you should terminate LEA bar to a common-mode voltage or tie it to ground via a pull-down resistor of 1k to 10k.

    4.        4.The inputs of ADCMP553 should also be a PECL value in order to produce an output that is also a PECL value.

     

    These are just some of those considerations. I’ll get back to you soon with a more detailed explanation.

     

    Somehow, I hope this helps.

     

    Regards,

    Anna

  • Hi Anna,

    Thanks for the response. I've attached an updated schematic incorporating your comments. In the schematic, the reset lines from the FPGA are normally tri-stated allowing the voltage output from Q/~Q to be transmitted to ~LE/LE. Initially Trigger is less than Trigger_Ref, so Q is low and LE is high (since Q is connected to ~LE and ~Q is connect to LE). When Trigger goes above the reference, Q goes high and LE goes low, latching the output. To clear the output, the FPGA brings ~LE low and LE high through a resistor divider network. Assuming that Trigger is now less than the reference, Q returns low and the FPGA tri-states the reset lines again.

    As far as I can tell, this should work correctly except for one possible problem. After the reset when Q returns low but while the FPGA reset lines are still being held high/low, the resistor divider network means that LE/~LE will end up outside the range specified in the datasheet. LE will be approx. 2.8V and ~LE ~1V, for a difference of 1.8V for 1 FPGA clock cycle  (~20ns).

    So here are my new questions: 1) Does my schematic seem to make sense? and 2) are the transient voltages on the LE pins tolerable? They are still within the Absolute Maximum Ratings but I'd like to make sure.

    Thanks for your feedback,

    -Schuyler

  • Schuyler - Did you ever implement this? Did it work?

    -Dave Elliott

  • Hi Dave - Sorry I missed this comment - haven't signed in for a while. Yes it did work. I needed to lower the overall resistance values, while keeping the ratios the same - I think the 10k became 1k. It ended up being able to latch signals that stayed high for ~1.5 ns. Shorter signals were not always captured.

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