ADN8810 SPI timing

Hello,

I have some questions about the SPI timing on the ADN8810 laser current source (hope this is the right place to ask, please let me know if not).

The background to this is that I would like to run the device at a high sample rate using back-to-back SPI transactions.  That is, the SPI should be clocked continuously and every clock cycle should transfer one bit of the 16-bit address/data word.

Based on the description of the serial data interface I am assuming that the /CS input is asynchronous (not sampled by SCLK) and  needs to be pulsed high for a minimum of 30 ns some time during the last SCLK cycle of each transaction (after the rising edge of SCLK on which D0 is sampled).  That being the case it looks possible to run back-to-back cycles if the /CS signal remains low except for a short high pulse during the last data bit of each 16-bit transaction.


  • Is this mode of operation feasible?  If not, what is the minimum required number of SCLK rising edges with /CS high?
  • Is the purpose of t5 (/CS High to SCLK High Setup) to define how early /CS must be negated to guarantee that a rising edge of SCLK does NOT clock data into the shift register?

Thanks in advance for your help.

Ian

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  • 0
    •  Analog Employees 
    on Feb 20, 2014 11:19 PM over 7 years ago

    Dear Ian,

     

    The ADN8810 uses a shared SPI bus for a serial communication. Yes, the /CS is an async control pin to select this device. The max. SCLK frequency is 12.5MHz.

     

    The ADN8810 datasheet has the timing specifications on page 5.

    Hope these timing specifications are sufficient for you to plan and configure your tests.

     

    Regarding about your questions, here are our initial answers:

    • Is this mode of operation feasible?  If not, what is the minimum required number of SCLK rising edges with /CS high?

      QA:     No. We need at least one min. required SCLK rising edge to enable the /CS.  

     

    • Is the purpose of t5 (/CS High to SCLK High Setup) to define how early /CS must be negated to guarantee that a rising edge of SCLK does NOT clock data into the shift register?

    QA:     Yes.

    What is your application to use this ADN8810? If you have further questions of how to use this ADN8810, welcome to contact me at dongfeng.zhao@analog.com.

     

    Best Regards,

     

    Dongfeng Zhao

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  • 0
    •  Analog Employees 
    on Feb 20, 2014 11:19 PM over 7 years ago

    Dear Ian,

     

    The ADN8810 uses a shared SPI bus for a serial communication. Yes, the /CS is an async control pin to select this device. The max. SCLK frequency is 12.5MHz.

     

    The ADN8810 datasheet has the timing specifications on page 5.

    Hope these timing specifications are sufficient for you to plan and configure your tests.

     

    Regarding about your questions, here are our initial answers:

    • Is this mode of operation feasible?  If not, what is the minimum required number of SCLK rising edges with /CS high?

      QA:     No. We need at least one min. required SCLK rising edge to enable the /CS.  

     

    • Is the purpose of t5 (/CS High to SCLK High Setup) to define how early /CS must be negated to guarantee that a rising edge of SCLK does NOT clock data into the shift register?

    QA:     Yes.

    What is your application to use this ADN8810? If you have further questions of how to use this ADN8810, welcome to contact me at dongfeng.zhao@analog.com.

     

    Best Regards,

     

    Dongfeng Zhao

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