We want know the reration of Figure 17 and Figure 19 in the AD8488 Data sheet
When CK_ENa became high , which clock does AD 8488 ouｔput mux-001 data ?
We want the all of timing chart
The arrows you show in the pdf are correct, the clocks are the same. As you can see, if each of the 128 data transfers were to be shown in a single timing diagram, the diagram would be very very long. That is why figure 19 is drawn as a detail of a very small segment of figure 17.
I hope this helps.
For Gated Clock A and Gated Clock B, it is shown 67 clocks. At which clock the data capture starts ? Will the data appear at output pin at rising edge of next clock. Please clarify what MUXCH001 signal is?