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ADN8810-Configuration of RESET and SB in Parallel Config.


i use 8 ADN8810 for additional output current, in a setup were i need up to 4 channels each with max. 600mA.

Each 2 ADN8810 for one Channel were assembelt like the example in the Datacheet:
But in there i dont get clearly information about pin SB and RESET in this
mode. Normaly they are set Aktive High or Low, cause they are negeted. But which state mades the ADN8810 to Process my Signal.

Reset on the 5V?

Regads Sebastian

  • Dear Sebastian,

    ADN8810 is a 5V device. You can either power it with +5V supply rail (positive supplied) or -5V supply
    rail (negative supplied).

    In your applications, two ADN8810s for one channel, you can program the two ADN8810s simultaneously by configuring the two devices with a same address, settled on pins: ADDR0 - 2. This address will be the part of SPI program frame.

    With this same address, the SCLK, SDA, and CS/ should be bonded in the way recommended in the datasheet fig. 18, to be programmed at the same time, via a SPI bus.

    SB/ and RESET/ are device feature control pins.

    SB/ allows you “Active Deactivates Output Stage (High Output Impedance State)”.


    RESET/ allows you “Asynchronous Reset to Return DAC Output to Code Zero; Active Low”

    In this way, you could bond two SB/ pins together to “Active Deactivates Output Stage (High
    Output Impedance State)” both ADN8810s at the same time, or use the two SB/ pins individually

    to “Active Deactivates Output Stage (High Output Impedance State)” one of the two ADN8810s

    per your system design.

    Same discussion (SB/ above ) applies to RESET/ signal, as well.

    Hope these are what you are looking for. Thanks for being interested in ADN8810.


    Best Regards,

    Dongfeng Zhao