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Finding the most appropriate comparator for a given pulse

Hello everyone,

I am currently working in the design of a discriminator for a photomultiplier, which is, an optical detector that exhibits a pulse of about 4-ns FWHM and a 100-mV peak voltage (see Image 1).

Image 1. Pulse waveform in persistence mode. Time scale is 10 ns/div.

So far, I have amplified this signal (see Image 2). I'm still having some issues with negative pulses and some offset in the amplfying stage, but that's not the topic I bring for support.

Image 2. A trail of amplified pulses.

I purchased and tested the ADCMP567 component and the ADCMP573 evaluation board. These are the results I have at the moment:

1. ADCMP573 evaluation board: I have used the suggested supply voltages at page 5 from its document, in which Vcci = 5 V, Vcco = 3.3 V, Vee = −5 V, for the PECL standard (2nd column). Then, I disabled the latch by connecting LE to Vcco-2V through a 510-ohm resistor and leaving LEB disconnected, as suggested by the datasheet. After that, I see the output voltages at the digital outputs go as expected (roughly 1 V for Q output and 1.4 V for complementary Q). However, digital outputs din't change their states. By the way, I have even tried to increase Vcco by making it the same as Vcci (5 V), but digital outputs didn't change.

Maybe this issue is similar to another one found in another thread.

Image 3. ADCMP573 outputs.

2. ADCMP567 component: I have designed a circuit using it. Its supply voltages are Vcci = 5V, Vcco = 3.3 V and Vee = -5.2 V. Again, the output voltages at the digital outputs go as expected (roughly 1.7 V for Q and 2.6 V for complementary Q, under the CML differential standard that has an 800mV output swing). When I use the signal from Image 2 as an input to compare, I see the Q output changes accordingly for a threshold adjusted to -1.37 V. Not all pulses will be discriminated, i.e., validated by their height and represented by an output digital pulse. In fact, I have observed that only the tallest analog pulses will be represented in the output.

Image 4. ADCMP567, one of the digital outputs in persistence mode. An attenuated 10x probe was used.

From testing both comparators, I'm making an educated guess: ADCMP567 and ADCMP573 have a not-so-broad bandwitdh as I've previously thought. As a consequence of it, both comparators need a much faster signal (above 3500 MHz), that also implies that it has a less than 1 nanosecond rise time. Also, they need a much higher slew rate than 50 V / microsecond (which is equivalent to 50 mV / nanosecond). 

After mentioning my experience with both comparators, I want to know if the ADCMP605 reference or another one may be more appropriate for my application, given the bandwidth (500 MHz) and slew rate (any?) given by the datasheet.


Maryam Correa

  • Hi Maryam,

    Apologies in the delay replying.

    Firstly I would like to be sure you are using the correct termination voltage for each comparator.

    The output termination for the ADCMP573 is 50ohm to VCCO - 2V. Are you using case 2 in  table 5 and using a scope terminated to 50ohm to GND?

    Also for the ADCMP567, to connect to a scope that has 50ohm to GND terminate you have terminate the device as follows:

    Are you using this configuration?

    On terms of bandwidth, trying a lower bandwidth part like the ADCMP605 could be useful but I try to ensure the termination setups are correct first.



  • Hi Stephen,

    Now I've taken a long time to reply, my apologies too.

    The oscilloscope I use is a low bandwidth one (200 MHz), with a 50-ohm input impedance. I used SMA cables and 50-ohm probes. I know this is not a good practice for proper sampling, but I don't have a faster oscilloscope. Then, I'll explain how I did the output configurations for both comparators:

    For the ADCMP573 reference, the 50-ohm termination goes to GND, like you commented.

    For the ADCMP567 reference, I didn't do any external termination. The ADCMP567 digital outputs (labeled as C1 and C2) went to a logic gate (SY55851A), which its differential inputs are terminated with a 100-ohm resistor between the true and complement pins.

    Image 1. Comparator wiring.

    Image 2. Logic gate wiring.

    For the ADCMP537 reference, is the 50-ohm termination correct? and, for the ADCMP567 reference, how should it be terminated with the SY55851A component?

    I'd like to know your thoughts for my case.



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