Post Go back to editing

AD8306 Logarithmic Amplifier Noise


I'm analyzing the signal to noise ratio of a system which includes an AD8306. I'm using the logarithmic amplifier output VLOG, and I'm interested in the noise contribution og the RSSI path. So basically I'm interested in the SNR as a function of the input voltage.

The noise contribution of the input stage (Inputs INHI, INLO) is stated in the datasheet. So the additive noise contribution for the "linear" path can be calculated straightforward.

To realize the logarithmic behaviour of the RSSI output, the detector cells have to be weighted/limited, leading in a different noise contribution of the single stages (depending on the input voltage). So I'm interested in the wheights of the detector cells. Further the ladder attenuation network at the beginning of the RSSI path and the corresponding four detector cells are not described closer.

In gerneral, I'm interested in the realization of the detector cells itself. According to the datasheet they are realized ba a full-wave detector, but how does this detector looks like (schematic). An ordinary full-wave rectifier (without additional capacitor) would end up in a time varing signal. So how is the DC signal generated.