Hi,

I'm analyzing the signal to noise ratio of a system which includes an AD8306. I'm using the logarithmic amplifier output VLOG, and I'm interested in the noise contribution og the RSSI path. So basically I'm interested in the SNR as a function of the input voltage.

The noise contribution of the input stage (Inputs INHI, INLO) is stated in the datasheet. So the additive noise contribution for the "linear" path can be calculated straightforward.

To realize the logarithmic behaviour of the RSSI output, the detector cells have to be weighted/limited, leading in a different noise contribution of the single stages (depending on the input voltage). So I'm interested in the wheights of the detector cells. Further the ladder attenuation network at the beginning of the RSSI path and the corresponding four detector cells are not described closer.

In gerneral, I'm interested in the realization of the detector cells itself. According to the datasheet they are realized ba a full-wave detector, but how does this detector looks like (schematic). An ordinary full-wave rectifier (without additional capacitor) would end up in a time varing signal. So how is the DC signal generated.

BR

Parents
• Hi,

I'm currenty analyzing the the log-amp cascaded amplifier/limiter chain according to the AD8309 datasheet (page 7-9). The results are looking promising, however the resulting trend is shifted towards a lower output voltage. My logarithmic analyze leads to an output trend similar to the attached image (figure 22 on page - 9 in AD8309 Datasheet). My solid (curved) trend is about 0.23V lower than the dashed straight one.

The dashed trend follows V_out = V_Y * 20 * log10(V_in/V_X) with values stated in the AD8306 datasheet.

• V_Y = 20 mV/dB
• V_X = 10^(-108 dBV/20) =  3.98 µV

According to the AD8309 datasheet, the knee Voltage E_k, the voltage level where the amplifier/limiter changes its amplification from A (4 = 12.04 dB) to 1, is obtained by

E_k = V_Y * 20*log10(A)/(A-1) = 80.3 mV

So it looks like I'm missing some kind of offset, which is responsible for the shift of the trend. I can't figure aut where this additive factor comes from.

Has anyone an idea?

• Hi,

I'm currenty analyzing the the log-amp cascaded amplifier/limiter chain according to the AD8309 datasheet (page 7-9). The results are looking promising, however the resulting trend is shifted towards a lower output voltage. My logarithmic analyze leads to an output trend similar to the attached image (figure 22 on page - 9 in AD8309 Datasheet). My solid (curved) trend is about 0.23V lower than the dashed straight one.

The dashed trend follows V_out = V_Y * 20 * log10(V_in/V_X) with values stated in the AD8306 datasheet.

• V_Y = 20 mV/dB
• V_X = 10^(-108 dBV/20) =  3.98 µV

According to the AD8309 datasheet, the knee Voltage E_k, the voltage level where the amplifier/limiter changes its amplification from A (4 = 12.04 dB) to 1, is obtained by

E_k = V_Y * 20*log10(A)/(A-1) = 80.3 mV

So it looks like I'm missing some kind of offset, which is responsible for the shift of the trend. I can't figure aut where this additive factor comes from.

Has anyone an idea?

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