ADA4961ACPZN Parallel Latched Mode Polarity and Timing


I’m going to use part number ADA4961ACPZN and control it via its parallel digital interface.

I plan to use the latched mode of operation for parallel control.

I couldn’t find a timing diagram in the datasheet for this mode, so I want to make sure I’m interpreting the text correctly.

In latched mode, should the LATCH signal be held high and pulsed low to update the gain setting?

Also, are the setup and hold times for latched mode consistent with the ones shown in the timing diagram for serial mode?


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    •  Analog Employees 
    on Feb 19, 2020 3:45 PM


      The parallel digital interface uses five binary bits (Bits[A4:A0]) and a latch pin. The LATCH pin controls whether the input data latch is transparent or latched. In transparent mode, gain changes as input gain control bits change. In latched mode, gain is determined by the latched gain setting and does not change with changing input gain control bits. (Page 16)


    Latch Input Asserts Parallel Gain Control. Logic 0 asserts transparent mode, and Logic 1 asserts latched mode. (Page 7)


    Connect the LATCH pin to a 3.3 V compliant logic control. Logic 0 asserts transparent mode, and Logic 1 asserts latched mode. (Basic Connection Page 18)

    LATCH=0 means changes on A[5:0] change the gain setting, and LATCH=1 means changes on A[5:0] will be ignored.  Here is a timing diagram I found in a design review.

    Warm Regards,


  • Hi Rachana,

    Thanks for the reply on this one.

    Your response suggests you included a timing diagram, but I’m not seeing one in the post.

     sent me an email showing a timing diagram (from another datasheet) so I think I understand the parallel latched mode interface.

    It seems like the ADA4961 datasheet should include a timing diagram for this mode to facilitate understanding.


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