Hi Friends,I am interested in one of your high-speed dual-channel comparator AD96687 and I would like to use it in one of our projects.We are not using the Latching function. so as per the datasheet, the Latch Enable pin should be Grounded Right?.Even after completing the datasheet, I don't have a clear idea of the latching operation of the chip.Can someone help me in solving this?
This comparator has differential latch mode input. These inputs must have different logical levels.
About disabling the latch function directly said:
Will this help you?
Yah, you got me. Now my doubt is should I keep the Latch Enable pin at 5V because 5V is my ECL logic high state in order to disable the latching capability. But as per the datasheet, the maximum voltage…
Classic ECL logic has a negative power supply of -5.2 volts. The logical element here is, in fact, a differential pair, one of the inputs of which is supplied with a reference voltage. This pair compares…
Thank you for your reply.
In the above circuit, if the transistor Q4 is on, my output will be about 4.4V and if it is off my output will be 5V.So my ECL logic high means 5V (I am not sure) and my swing will be about 0.7V.
Thank you for your time.
I don't understand whether you mean one of the Latch Enable inputs or the Comparator inputs to be grounded to disable the latching operation.
In the datasheet, it is said that we need to ground the Latch Enable pin to disable the latching operation. The ground is the ECL logic high state.
I don't want to use the latching operation for my first compactor. So I connected the Latch Enable pin to +5V through a resistor since +5V is the logic high state and its complimentary pin is left to float. My ECL is swinging between +4.4V and +5V.
I want the second comparator to be latched based on the output of the first comparator.
I have found another chip ADCMP551BRQZ of Analog Devices with the same application and is PECL. Do you think this chip is more suitable for my purpose?.
Now this circuit seems much better to me. But you're talking about your ECL logic. Do I understand correctly that you want to use some special logic on discrete components and connect it to this comparator?
Because if you were using a standard ECL series, you wouldn't be asking these questions. This connects directly to each other.
First, please draw a more detailed circuit where these two parts are connected to each other:
Because I'm confused.
email@example.com said:I don't understand whether you mean one of the Latch Enable inputs or the Comparator inputs to be grounded to disable the latching operation
The "lower floor" of the internal circuit of this comparator is the logical part. Here's what it looks like:
You can see that the logic input ground is interpreted as a logic level because the ground potential is higher than the Vr reference voltage. I hope this will clarify something for you
The positive supply voltage is used by the analog comparator circuit itself. I understand this intuitively. Unfortunately, the Analog Devices application engineers don't participate in this discussion and can't tell if I'm right or wrong.
Thank You for your reply.The ECL I am using is single-ended not a differential and my doubt is can I use PECL with AD9687.Also, I have seen another chip ADCMP551BRQZ of Analog Devices. Can I use this chip for my application?.
firstname.lastname@example.org said:my doubt is can I use PECL with AD9687.
PECL and ECL are mirror images of each other. In principle, this looks possible, but you should move the AD96687 output signals up, above the ground potential.
Obviously, your cryptic single-ended logic has logical thresholds. There is a maximum voltage that will be reliably perceived as a logical 1 and there is a minimum voltage that will be reliably perceived as a logical 0.
You have given very little information, and so far I can't say anything specific.