AD96687 Designing

Hi Friends,
I am interested in one of your high-speed dual-channel comparator AD96687 and I would like to use it in one of our projects.
We are not using the Latching function. so as per the datasheet, the Latch Enable pin should be Grounded Right?.
Even after completing the datasheet, I don't have a clear idea of the latching operation of the chip.
Can someone help me in solving this?


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  • Classic ECL logic has a negative power supply of -5.2 volts. The logical element here is, in fact, a differential pair, one of the inputs of which is supplied with a reference voltage. This pair compares the input voltage with the reference voltage. The reference voltage here is minus 1.3 volts.

    Once again pay attention to the logical levels

    An input voltage higher than -1.3 volts is interpreted as logic 1. Ground voltage also is logic 1

    Therefore, your converter must translate the input logic level below ground potential. Can you do that?

  • Ok. I understood what you are saying.
    But for my requirement, the ECL is switching between 5V and 4.4V and you can see it from my circuit provided.
    My doubt is can I keep my Latch Enable pin at 5V to disable the latching operation?. 

  • Of course, exceeding absolute maximum ratings is a bad idea in itself. But I believe that you can use a voltage source of 5 volts but provided that you limit the current.

    If it is said that the maximum current of the logic 1 is 40 μA, then ,in other words, this is quite enough to enable the function. Limit the current to about 40 µA using a resistor.

    If you need to control the latch function, you need to lower the control input potential below the ground potential. If you only need to disable this function, you can use a pull-up resistor.

  • Thank You for your reply.


    In the above circuit, I am using a 2 Channel Latching comparator AD96687.
    I want the latching capability of comparator1 to be disabled, and comparator2 should be latched based on the output of comparator1. Is the circuit I provided apt for my requirement ?.

  • Now I see that you only need to disable the latch function. But I have a few comments about your circuit.

    To disable the latch function, it is enough to pull one of the corresponding inputs to the ground, why don't you use this? And if you want to pull it up to +5 volts, you need to limit the current flowing in. Applying a voltage higher than the ground potential to the logic input will cause a direct bias of the base-collector junction of the input transistor. This will result in a significant input current that may cause damage. And even if it does not cause damage, such a significant input current is not necessary for correct operation.

    ECL logic has high-resistance pull-down resistors at the inputs, so it is acceptable to leave the inputs floating. It's good.

    Do you use the output of the first comparator for control, but you don't use load resistors? The ECL logic outputs are an open collector, and pull-down resistors are required. This may work with internal resistors on the Latch Enable inputs, but you will not be able to take advantage of the high speed of this comparator.

    If you connect these outputs to the inputs with as short wires as possible, you can avoid the complexities of designing microwave lines. But for a quick recharge of parasitic capacitances, the presence of load resistors at the outputs is mandatory.

    If these resistors have a low resistance, say 50 or 75 ohms, it is advantageous to connect them to an additional power supply of -2 volts, to reduce the power dissipation. In your case, such low-value resistors are not required here, so it is possible to connect them to -5.2 volts directly. I would recommend a value of, say, 240 ohms. 

    Please tell me about the practical results.

    Regards,

    Kirill